PLL detection circuit with lock judgement circuit

Details PLL detection circuit with lock judgement circuit PLL detection circuit with lock judgement circuit

2000-07-24

2002-05-28

Grimm, Siegried H. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331SDIG002, C331S025000, C348S536000, C348S731000, C348S735000, C455S234100, C455S182300

Reexamination Certificate

active

06396354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to PLL detection circuits such as those used in radios, television receivers, satellite broadcast receivers, video recorders, receivers of mobile communication systems, and like apparatuses.
2. Description of the Related Art
In synchronous detection receivers such as television receivers, an oscillation signal that is synchronized with a video intermediate frequency (hereinafter abbreviated as VIF) signal obtained by, for example, a tuner or a frequency conversion circuit is generated by using a PLL circuit. The VIF signal is synchronously detected by using the generated oscillation signal and a video detection signal is thereby output.
FIG. 11
is a block diagram showing the main part of a detection circuit using a PLL detection circuit of a television receiver.
As shown in the figure, this detection circuit is composed of a PLL circuit that consists of a phase comparator
10
, a low-pass filter
20
, and a voltage-controlled oscillator (VCO)
30
, an AGC (automatic gain control) amplifier (AGC AMP)
50
, an AGC control circuit
60
, an amplitude detector (AM detector)
70
, a comparator
80
, an AGC loop filter
90
, a low-pass filter
110
, and a PLL lock judgment circuit
120
.
An input signal S
IN
that is input to the AGC amplifier
50
is an intermediate frequency signal that has been produced through conversion into a video intermediate frequency VIF by a frequency conversion circuit, for example. The video intermediate frequency depends on the broadcast system. For example, it is 58.75 MHz in the NTSC scheme that is employed in Japan and other regions.
The video intermediate frequency signal S
IN
is amplified by the AGC amplifier
50
, and an amplified signal S
A
is supplied to the phase comparator
10
and the AM detector
70
. Since the gain of the AGC amplifier
50
is controlled in accordance with a control signal S
C
that is supplied from the AGC control circuit
60
, the amplitude of the amplified signal S
A
is kept approximately constant irrespective of the magnitude of the input signal.
The phase comparator
10
, the low-pass filter
20
, and the VCO
30
constitute the PLL circuit. The phase comparator
10
compares the phase of the amplified signal S
A
with the phase of an output signal S
L
of the VCO
30
and produces a phase error signal S
10
based on a phase error between those signals. The low-pass filter
20
attenuates high-frequency components of the phase error signal S
10
, extracts a low-frequency component in a prescribed frequency band, and supplies it to the VCO
30
as a frequency control signal. The VCO
30
controls the oscillation frequency in accordance with the frequency control signal supplied from the low-pass filter
20
, and supplies an oscillation signal S
L
to the phase comparator
10
and the AM detector
70
.
In this manner, the oscillation signal S
L
whose frequency varies following the frequency of the output signal S
A
of the AGC amplifier
50
can be generated by the PLL circuit that consists of the phase comparator
10
, the low-pass filter
20
, and the VCO
30
. That is, the oscillation signal S
L
that is completely phase-synchronized with the input signal is generated inside the detection circuit. The AM detector
70
performs synchronous detection by using the sync signal S
L
by, for example, multiplying together the amplified signal S
A
of the AGC amplifier
50
and the oscillation signal S
L
, and outputs a video detection signal S
PD
that varies in accordance with the amplitude of the signal S
A
.
As shown in
FIG. 11
, the video detection signal S
PD
obtained by the AM detector
70
is supplied to the low-pass filter
110
and the comparator
80
.
The comparator
80
compares the video detection signal S
PD
with a reference voltage V
1
and supplies a comparison result to the AGC loop filter
90
.
For example, the AGC loop filter
90
has a low-pass filter characteristic. The AGC loop filter
90
extracts a signal in a prescribed low-frequency band from the output signal of the comparator
80
and supplies the extracted signal to the AGC control circuit
60
and the PLL lock judgment circuit
120
as an AGC control signal S
AGC
.
The AGC control circuit outputs, in accordance with the AGC control signal S
AGC
, the control signal S
c
to be used for controlling the gain of the AGC amplifier
50
. That is, in the detection circuit, a feedback loop is formed in which the gain of the AGC amplifier
50
is controlled in accordance with the video detection signal S
PD
that is output from the AM detector
70
. Through the control of the feedback loop, the gain of the AGC amplifier
50
is controlled automatically so that the detection output level is kept approximately constant.
The PLL lock judgment circuit
120
outputs a PLL lock judgment signal S
K
indicating whether the PLL circuit consisting of the phase comparator
10
, the low-pass filter
20
, and the VCO
30
is in a lock state in accordance with the low-pass filter
110
and the AGC control signal S
AGC
.
Incidentally, in the above conventional detection circuit, the PLL lock judgment is performed in accordance with the level of the video detection signal S
PD
and the state of the AGC control signal S
AGC
. That is, whether the PLL circuit is in a lock state is judged based on the operation state of the entire detection system rather than the operation state of the PLL circuit itself. This results in a disadvantage that when an unexpected signal is input or in a transition state as occurs after the power is turned on, the operation of the detection circuit is prone to become unstable owing to an erroneous PLL lock judgment; there is fear of erroneous operation of a receiving circuit.
The present invention has been made in view of the above circumstances, and an object of the invention is therefore to provide a PLL detection circuit that can improve the stability of operation in a transition state, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly.
SUMMARY OF THE INVENTION
To attain the above objects, a PLL detection circuit according to the invention comprises a PLL circuit including a phase comparison circuit for comparing phases of an input signal and an oscillation signal and outputting a phase error signal corresponding to a phase error between the input signal and the oscillation signal based on a result of the comparison, and an oscillation circuit for generating the oscillation signal while controlling an oscillation frequency in accordance with the phase error signal; a PLL lock judgment circuit for judging whether the PLL circuit is in a lock state based on the phase error signal in such a manner as to judge that the PLL circuit is in a lock state if a voltage level of the phase error signal is in a prescribed range and to judge that the PLL circuit is out of a lock state if the voltage level of the phase error signal is out of the prescribed range; and a selection circuit for selecting a signal corresponding to the phase error signal, for example, an amplified signal produced by amplifying the phase error signal, or a voltage signal having a prescribed level in accordance with a judgment result of the PLL lock judgment circuit, and outputting the selected signal as an AFT control signal.
Another PLL detection circuit according to the invention comprises an AGC amplification circuit for amplifying an input signal at a prescribed gain; a PLL circuit including a phase comparison circuit for comparing phases of an output signal of the AGC amplification circuit and an oscillation signal and outputting a phase error signal corresponding to a phase error between the input signal and the oscillation signal based on a result of the comparison, and an oscillation circuit for generating the oscillation signal while controlling an oscillation frequency in accordance with the phase error signal; a PLL lock judgment circuit for judging whether the PLL circuit including the phase comparison circuit and the oscillation circuit is in

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