PLL clock signal regenerator using a phase correlator

Details PLL clock signal regenerator using a phase correlator PLL clock signal regenerator using a phase correlator

1990-07-23

1992-05-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307516, 328133, 328155, 331 12, 331 27, 375120, H03L 7087

Patent

active

051152088

ABSTRACT:
A circuit for the regeneration of the clock signal within a message containing a preamble and random data. No assumption as to the message structure is required for the operation of such a circuit. The circuit operates on an autocorrelation principle which allows a voltage controlled oscillator (VCO) which is used to reconstruct the clock signal to operate free of the data format. The device is essentially formed as a phase correlator connected to a feedback loop which contains in series a filter, an amplifier and a voltage controlled oscillator. The correlator is formed by a delay line feeding a delayed data signal to two multipliers. The data is also fed to a shift register, the output of which is also fed to the multipliers. The multiplier outputs are fed to a differentiating element which outputs an error signal which acts as a clock correction signal feeding the VCO which, when necessary, adjusts the VCO output so as to match the clocking within the circuit with the clock timing of the message received.

REFERENCES:
patent: 3961273 (1976-06-01), Trush
patent: 4151463 (1979-04-01), Kibler
patent: 4422176 (1983-12-01), Summers

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