PLL clock generator integrated with microprocessor

Details PLL clock generator integrated with microprocessor PLL clock generator integrated with microprocessor

1992-03-31

1995-05-02

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

331 1A, 331 57, H03L 7099, H03B 502

Patent

active

054123496

ABSTRACT:
A PLL based deskewed clock generator which may be fully integrated on a microprocessor is disclosed. The clock generator has a skew of less than 0.1 ns with peak to peak jitter of 0.3 ns using a 0.8 .mu.m CMOS technology. The PLL comprises a phase frequency detector, charge pump, loop filter and voltage controlled oscillator from which the internal clock is generated. Since the PLL is on the same chip as the microprocessor, it is difficult to isolate the PLL from the noise generated by the microprocessor core logic and output buffers. Without an external filter, noise from the motherboard also influences the PLL. Power supply noise can cause a direct change in the frequency of the voltage controlled oscillator of the PLL. Circuits which overcome the adverse effects which would be created by such noises are also described.

REFERENCES:
patent: 3493884 (1970-02-01), Kulp
patent: 4689581 (1987-08-01), Talbot
patent: 4847516 (1989-07-01), Fujita et al.
patent: 5122679 (1992-06-01), Ishii et al.
patent: 5272453 (1993-12-01), Traynor et al.
patent: 5294894 (1994-03-01), Gebara

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