PLL clock generator having trimmable frequency dividers

Details PLL clock generator having trimmable frequency dividers PLL clock generator having trimmable frequency dividers

1997-11-12

1999-03-02

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, 377 29, 377110, H03L 718

Patent

active

058776575

ABSTRACT:
A reference clock signal oscillator generates a reference clock signal. A first programmable counter performs frequency dividing on the reference clock signal and outputs a reference signal resulting-from the frequency dividing. A voltage controlled oscillator generates an output clock signal, the frequency of which is controllable by input voltage control. A second programmable counter performs frequency dividing on the output clock signal and outputs a feedback signal resulting from the frequency dividing. A phase comparator compares the reference signal and the feedback signal, and outputs a phase difference signal which is based on the phase difference between the phases of the reference signal and the feedback signal. A driving circuit includes a charge pump and a loop filter and generates a signal to be applied to the voltage controlled oscillator based on the phase difference signal and performs filtering on the signal to be applied to the voltage controlled oscillator. At least one trimming switch unit determines, by trimming, the frequency dividing ratio of at least one of the first and second programmable counters.

REFERENCES:
patent: 4654859 (1987-03-01), Kung et al.
patent: 5036216 (1991-07-01), Hohmann et al.
patent: 5244836 (1993-09-01), Lim
patent: 5339050 (1994-08-01), Llewllyn
patent: 5420545 (1995-05-01), Davis et al.
patent: 5641701 (1997-06-01), Fukuhara et al.
Abstract of Japanese Publication No. 63-48838 (Mar. 1, 1988).
Abstract of Japanese Publication No. 59-124741 (Jul. 18, 1984).

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