PLL circuit with self-selecting variable divide ratio

Details PLL circuit with self-selecting variable divide ratio PLL circuit with self-selecting variable divide ratio

2007-07-17

2007-07-17

Chang, Joseph (Department: 2817)

Oscillators

With frequency adjusting means

Step-frequency change

C331S016000, C331S017000, C331S034000, C331S044000

Reexamination Certificate

active

11217183

ABSTRACT:
A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO's oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

REFERENCES:
patent: 6806786 (2004-10-01), Lam et al.
patent: 2005/0116781 (2005-06-01), Yamamoto et al.
patent: 2005/0237119 (2005-10-01), Irie

Affiliated with

Also associated with

Rating

PLL circuit with self-selecting variable divide ratio does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL circuit with self-selecting variable divide ratio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL circuit with self-selecting variable divide ratio will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3727576