PLL circuit with non-volatile memory

Details PLL circuit with non-volatile memory PLL circuit with non-volatile memory

1997-08-27

1999-06-08

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327159, 327148, 327157, 331 1A, 331 16, 331DIG2, 331DIG3, 375374, H03L 7183, H03L 7089

Patent

active

059107413

ABSTRACT:
To provide a PLL circuit with little jitter and a minimum frequency drawing time, a PLL circuit comprises: a phase comparator for generating an up-down signal, which is turned to logic HIGH when a reference clock signal is phase-advanced to an output clock signal and a phase lock signal, indicating synchronization of the output clock signal to the reference clock signal; a timing signal generator for generating a timing signal when the phase lock signal is generated for a certain period after said timing signal generator is initialized with a reset signal; an up-down counter for generating a count value which is incremented when the up-down signal is at logic HIGH and decremented when the up-down signal is at logic LOW according to each pulse of a count clock, memorizing the count value in a nonvolatile memory when controlled by the timing signal, and outputting the memorized count value when initialized by the reset signal; a D/A converter for outputting a control voltage in proportion to the count value; and a VCO for providing the output clock signal according to the control voltage.

REFERENCES:
patent: 4703520 (1987-10-01), Rozanski, Jr. et al.
patent: 5422911 (1995-06-01), Barrett, Jr. et al.
patent: 5608355 (1997-03-01), Noguchi
patent: 5703540 (1997-12-01), Gazda et al.
patent: 5757238 (1998-05-01), Ferraiolo et al.

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