PLL circuit which compensates for stoppage of PLL operations

Details PLL circuit which compensates for stoppage of PLL operations PLL circuit which compensates for stoppage of PLL operations

2001-07-23

2004-07-27

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C331S025000, C331SDIG002

Reexamination Certificate

active

06768357

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a PLL circuit which generates and outputs a frequency signal which has a predetermined relationship with a reference frequency signal, and in particular, to a PLL circuit which enacts countermeasures in cases in which PLL operation stops.
BACKGROUND TECHNOLOGY
As illustrated in
FIG. 7
, in a PLL circuit, phases of a reference signal fr and a comparison signal fc are compared at a phase comparator
101
which is formed by an exclusive OR circuit or the like. The signal of the results of comparison is smoothed at a loop filter
102
to become a control voltage Vc. The frequency oscillated by a voltage control oscillator (VCO)
103
is controlled by this control voltage Vc, and the frequency signal fck obtained thereat is the output frequency signal. This output frequency signal fck is inputted to a frequency divider
104
, and there, the frequency is made to be 1/N and the resulting signal is inputted as the comparison signal fc to the phase comparator
101
.
At the PLL circuit, the entire circuit is operated such that, given that the frequency of the reference signal fr is fr, the frequency of the comparison signal fc is fc, and the frequency of the oscillation frequency signal fck is fck, in a synchronized state, the relational formulas
fr ≅fc, fc=fck/N
are satisfied, such that the comparison signal fc always follows the reference signal fr.
When an analog image signal is digitally processed, a PLL circuit such as that described above is used in order to generate a sampling clock. The frequency of the sampling clock extends over a wide range of from 10 MHz to 100 MHz or more depending on the type of image signal.
Therefore, there are cases in which it is demanded of the voltage control oscillator
103
that the maximum/minimum frequency ratio of the oscillation frequency thereof is two times or more, and that the oscillation frequency is greater frequency range that can cover such cases is used.
However, in a PLL circuit having a voltage control oscillator of such a wide frequency range, when the oscillation frequency is higher than needed, the circuit of a portion which forms the PLL circuit may not able to follow, and PLL operation may stop. Such a situation occurs, for example, when the reference signal fr changes suddenly (the input signal becomes on/off, or the like) and the oscillation frequency varies greatly until a synchronized stable state is reached, or when the frequency of the reference signal fr is increased greatly and the oscillation frequency is increased, and the like.
In such cases, the frequency dividing operation of the frequency dividing circuit
104
is not able to follow, and the output signal, i.e., the comparison signal fc, disappears. Thus, the phase comparator
101
judges that the oscillation frequency of the voltage control oscillator
103
has fallen, operates such that the oscillation frequency is increased, and boosts the control voltage Vc to the maximum oscillation frequency. When such a state arises, even if this state is temporary, it is impossible for operation to return to normal by itself.
Therefore, conventionally, in order to have the oscillation frequency fck of the voltage control oscillator
103
not exceed the operating limit frequencies of the other circuits forming the PLL circuit, a voltage limiting circuit
105
such as that illustrated in
FIG. 8
was inserted between the voltage control oscillator
103
and the loop filter
102
, so as to provide an upper limit for the control voltage Vc.
In the voltage limiting circuit
105
of
FIG. 8
, the maximum value of the control voltage Vc is limited by a voltage-regulator diode ZD, and, as illustrated in
FIG. 9
, the oscillation frequency of the voltage control oscillator
103
is limited to fd which is sufficiently lower than the maximum value fmax. As a result, the frequency fck, which oscillates at the voltage control oscillator
103
, is in the range from the minimum frequency fmin to the upper limit frequency fd, and the above-described problem can be avoided.
However, in a method in which the control voltage Vc inputted to the voltage control oscillator
103
is directly limited by the voltage limiting circuit
105
in this way, there were the problems that the dispersion in the characteristics of the voltage-regulator diode ZD which is the limiting element of the voltage limiting circuit
105
, and the dispersion in the oscillation frequency fck at the voltage control oscillator
103
with respect to the control voltage Vc, had to be newly corrected, and further, that the oscillation frequency of the PLL circuit had to be limited with sufficient margin from the operation frequency (target frequency) of the PLL circuit.
Therefore, an object of the present invention is to provide a PLL circuit which can easily return to normal, even if the voltage control oscillator oscillates abnormally and PLL operation stops.
DISCLOSURE OF THE INVENTION
In the present invention, a PLL circuit in which a phase comparator, a loop filter, a voltage control oscillator and a frequency divider are successively loop-connected, comprises: operation stoppage detecting means for detecting that PLL operation has stopped; and control means for, when said operation stoppage detecting means detects stoppage of operation, controlling the voltage control oscillator such that an oscillation frequency of the voltage control oscillator is low. In this way, when the oscillation frequency of the voltage control oscillator exceeds a predetermined value and the PLL circuit stops operating, operation can quickly be returned to normal by a simple structure.


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