PLL circuit which can reduce phase offset without increase...

Details PLL circuit which can reduce phase offset without increase... PLL circuit which can reduce phase offset without increase...

2000-10-17

2001-11-20

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000

Reexamination Certificate

active

06320435

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit. More particularly, the present invention relates to the PLL circuit for reducing a phase offset without an increase in an operation voltage.
2. Description of the Related Art
Conventionally, a PLL circuit has been known as one of basic techniques used in various fields, for example, such as information processing, communication and the like. This conventional PLL circuit, whose example is shown in
FIG. 1
, is provided with a phase frequency comparator
50
, a charge pump
51
, a loop filter
52
, a voltage current converter
53
, a current control oscillator
54
and a feedback frequency divider
55
.
The phase frequency comparator
50
compares a phase and a frequency of an input signal f
REF
with those of a feedback signal f
FB
outputted from the feedback frequency divider
55
, respectively, to generate one of an increase signal UP and a decrease signal DOWN which indicate errors between both the signals. For example, a clock signal from an oscillator (not shown) is used as the input signal f
REF
The increase signal UP generated by the phase frequency comparator
50
has a pulse width corresponding to a phase delay and a frequency drop of the feedback signal f
FB
with respect to the input signal f
REF
. Also, the decrease signal DOWN has a pulse width corresponding to a phase advance or leading and a frequency rise or increase of the feedback signal f
FB
with respect to the input signal f
REF
. The increase signal UP and the decrease signal DOWN which are generated by the phase frequency comparator
50
are sent to the charge pump
51
.
The charge pump
51
is a charge pump of a single output. The charge pump
51
generates the current pulses corresponding to the respective pulse widths of the increase signal UP and the decrease signal DOWN to send to the loop filter
52
. The loop filter
52
has a resistor R
2
and capacitors C
4
, C
5
. The loop filter
52
accumulates charges in the capacitors C
4
, C
5
, in response to the current pulses sent by the charge pump
51
, and discharges the charges accumulated in the capacitors C
4
,C
5
, and then generates the voltages corresponding to the current pulses. The voltages generated by the loop filter
52
are sent to the voltage current converter
53
.
The voltage current converter
53
converts the voltage outputted from the loop filter
52
into a current to send to the current control oscillator
54
. The current control oscillator
54
generates a signal oscillating at a frequency corresponding to a value of the current sent by the voltage current converter
53
. The current control oscillator
54
oscillates at a frequency equal to N times the frequency of the input signal f
REF
at a lock state. The signal generated by the current control oscillator
54
is outputted to external portion as an output signal f
OUT
of the PLL circuit, and sent to the feedback frequency divider
55
. The feedback frequency divider
55
performs a frequency division into 1/N on the output signal f
OUT
to generate the feedback signal f
FB
and send the feedback signal f
FB
to the phase frequency comparator
50
.
The operations of the conventional PLL circuit having the above-mentioned configuration will be described below. Let us suppose that a phase of the feedback signal f
FB
fed back to the phase frequency comparator
50
from the feedback frequency divider
55
is more delayed than a phase of the input signal f
REF
.
In this case, the phase frequency comparator
50
generates the increase signal UP having the pulse width corresponding to the frequency drop and the phase delay to send to the charge pump
51
. The charge pump
51
sends out a current corresponding to the increase signal UP, and charges the capacitors C
4
, C
5
of the loop filter
52
. Thus, the voltage generated by the loop filter
52
is made higher, which thereby increases the current outputted by the voltage current converter
53
. This results in a rise of an oscillation frequency of the output signal f
OUT
outputted by the current control oscillator
54
. Also, a phase of the output signal f
OUT
is advanced to thereby approach a phase of the input signal f
REF
.
On the other hand, the case in which the phase of the feedback signal F
FB
is more advanced than a phase of the input signal f
REF
will be described below.
In this case, the phase frequency comparator
50
generates the decrease signal DOWN having the pulse width corresponding to the frequency rise and the phase advance to send to the charge pump
51
. So, the charge pump
51
pulls the current corresponding to the decrease signal DOWN, and discharges the capacitors C
4
, C
5
of the loop filter
52
. Thus, the voltage outputted by the loop filter
52
is made lower, which thereby decreases the current outputted by the voltage current converter
53
. This results in the drop in the oscillation frequency of the output signal f
OUT
outputted by the current control oscillator
54
. Also, the phase of the output signal f
OUT
is delayed to thereby approach the phase of the input signal f
REF
.
As mentioned above, the PLL circuit always compares the phase and the frequency of the output signal f
OUT
with those of the input signal f
REF
, respectively. If there is the phase delay or the phase advance in the output signal f
OUT
with respect to the input signal f
REF
, the feedback control is carried out so as to correct it. If the phase delay or the phase advance is converged within a predetermined range, the phase frequency comparator
50
generates the increase signal UP and the decrease signal DOWN having the same short pulse width. Thus, the amounts of the charges which are charged and discharged in the capacitors C
4
, C
5
of the loop filter
52
are equal to each other and balanced so that the PLL circuit becomes at the lock state.
At this lock state, the phase and the frequency of the output signal f
OUT
coincide with those of the input signal f
REF
, respectively. By the way, the charge pump
51
typically has a dead band, in which the charges are never charged and discharged unless there is a phase difference greater than a certain value, with regard to the relation between the phase difference, namely, the phase delay or the phase advance and the amount of the charge to be charged or discharged. Thus, it is designed such that the increase signal and the decrease signal having the same pulse width are generated even at the lock state.
The configuration example of another conventional PLL circuit will be described below with reference to FIG.
2
.
A charge pump
61
used in this PLL circuit is a differential output pump. That is, the charge pump
61
generates a current pulse OUT
1
corresponding to a pulse width of an increase signal UP and a current pulse OUT
2
corresponding to a pulse width of a decrease signal DOWN, and sends to a first loop filter
62
A and a second loop filter
62
B, respectively. The configurations and the operations of the first loop filter
62
A and the second loop filter
62
B are equal to those of the above-mentioned loop filter
52
. Then, a voltage current converter
53
converts a potential difference between a signal outputted from the first loop filter
62
A and a signal outputted from the second loop filter
62
B into a current signal.
According to this PLL circuit, the noise components of a power supply noise, a coupling noise to circuits except the loop filters and the like included in each of the first loop filter
62
A and the second loop filter
62
B are equal with each other, and the noise as a whole is cancelled out by the voltage current converter
53
. That is, the above-mentioned noise has no influence on the potential difference between the first loop filter
62
A and the second loop filter
62
B, which leads to the merit of generating the PLL circuit strong in the noise.
By the way, in
FIGS. 1 and 2
, the capacitors C
5
, C
5
, are mounted so as to weaken a sharp change in a signal waveform caused by a pulse noise or a

Affiliated with

Also associated with

Rating

PLL circuit which can reduce phase offset without increase... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL circuit which can reduce phase offset without increase..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL circuit which can reduce phase offset without increase... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2571357