PLL circuit used temperature compensated VCO

Details PLL circuit used temperature compensated VCO PLL circuit used temperature compensated VCO

1999-12-30

2002-01-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S512000

Reexamination Certificate

active

06342798

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to phase-locked loop (PLL) circuit which includes a temperature compensated voltage controlled oscillator (VCO) whose frequency stability is not influenced greatly, even when an ambient temperature changes.
DESCRIPTION OF THE RELATED ART
Generally, a PLL circuit consists of a phase comparator, a frequency comparator, a loop filter, a VCO and other required components. The pull-in range/lock range of the phase comparator is not usually wide, and in the event the dispersion of the oscillating frequencies of the VCO becomes large due to changes of the ambient temperature and manufacturing conditions of the VCO, a designated frequency may not be pulled in.
In order to prevent this problem, the frequency comparator may be used to widen the pull-in range. However, in the event the oscillating frequency of the VCO is largely different from a designated frequency, the designated frequency can not be pulled in. In this case, a reference clock of high accuracy, such as a quartz crystal oscillator, is needed.
In the event that inputted data is interrupted, the VCO operates at a frequency shifted largely from the designated frequency. Therefore, when data is inputted again, it takes a long time for the PLL circuit to lock again, that is, the pull-in time becomes long.
In order to solve this problem, Japanese Patent Application Laid-Open No. HEI 8-265146 discloses a PLL circuit. In this application, resistors and a thermistor are connected in series, and by changing the source from which an output voltage is obtained, one of the offset voltages, which have different gradients to compensate for varying temperature characteristics of the VCO, is outputted.
FIG. 1
is a block diagram showing a basic constitution of a convention PLL circuit. As shown in
FIG. 1
, the conventional PLL circuit consists of a voltage generator
10
, a VCO
20
, a temperature compensating circuit
30
, a phase comparator
40
, a loop filter
50
, a reference frequency signal oscillator
60
and a frequency divider
70
. In this circuit, the voltage generator
10
detects an ambient temperature and generates a voltage value in response to the ambient temperature, and outputs the voltage value to the temperature compensating circuit
30
.
The temperature compensating circuit
30
compensates for the change of the modulation sensitivity of the VCO
20
based on the voltage value outputted from the voltage generator
10
. Actually, the temperature compensating circuit
30
adjusts the voltage by the value of the output of the phase comparator
40
so that the multiplied value of the sensitivity value of the phase comparator
40
and the modulation sensitivity value of the VCO
20
remains a constant value regardless of the ambient temperature.
By this operation, even when the modulation sensitivity of the VCO
20
changes due to the change of the ambient temperature, the changes of the intrinsic frequency and the dumping constant are prevented. With this, the occurrence of bad influences, such as increasing the phase noise, making the pull-in time long and lessening the stability, are prevented.
FIG. 2
is a graph showing a modulation sensitivity of the VCO
20
of the conventional PLL circuit. As shown in
FIG. 2
, the modulation sensitivity changes when the ambient temperature changes, and these changes have two types. One type L
1
occurs when the modulation sensitivity increases in response to the increase of the ambient temperature. The other type L
2
occurs when the modulation sensitivity decreases in response to the increase of the ambient temperature.
FIGS. 3A and 3B
are diagrams showing constitutions of the voltage generator
10
of the conventional PLL circuit. The voltage generator
10
consists of resistors R
1
and R
2
, and a thermistor TH
1
. As shown in
FIG. 3B
, with a temperature sensitivity of the type L
1
shown in
FIG. 2
in which the modulation sensitivity of the VCO
20
increases in response to an increase in the ambient temperature, the voltage is outputted from a point between the thermistor TH
1
and the resistor R
2
. And as shown in
FIG. 3A
, with a temperature sensitivity of the type L
2
shown in
FIG. 2
in which the modulation sensitivity of the VCO
20
decreases in response to an increase in the ambient temperature, the voltage is outputted from the point between the thermistor TH
1
and the resistor R
1
.
However, in this conventional PLL circuit, in the event that the dispersion of the modulation sensitivity of the VCO occurs due to a dispersion of the manufacturing conditions of the VCO, the gradient of the thermistor value must be adjusted again. Moreover, in an optical receiver used for optical communication, the PLL circuit is used under a wide range of ambient temperature conditions from −40 to +85° C. In this case, the modulation sensitivity of the VCO is not always linear as shown in FIG.
2
. There is a problem in that the temperature compensation may not be performed by the generation of voltages as shown in
FIGS. 3A and 3B
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a PLL circuit including a temperature compensated VCO, in which an oscillating frequency of the VCO is controlled to be within a pull-in range of a phase comparator by applying an external voltage to an input voltage of the VCO beforehand, in order to prevent the problem mentioned above. Further, the present invention provides a PLL circuit including a temperature compensated VCO, which provides a temperature/voltage converter that generates an optimal external control voltage in response to a change in the ambient temperature, and in which the VCO is always controlled to oscillate within the pull-in range of the phase comparator.
According to a first aspect of the present invention, for achieving the object mentioned above, a PLL circuit including a temperature compensated VCO, in which phases and frequencies of the VCO are synchronized with inputted data, provides a phase comparing means for detecting phase shifts of said inputted data and of signals outputted from said VCO from optimal signals, and for outputting control signals based on the detected results, a signal smoothing means for smoothing said control signals and outputting said smoothed signals to said VCO, and a temperature/voltage converting means for outputting beforehand said VCO external control voltages, with which said VCO oscillates within a pull-in range of said phase comparing means.
According to the second aspect of the present invention, in the first aspect, said temperature/voltage converting means provides a temperature sensor for sensing an ambient temperature, an analog/digital converter for converting said sensed ambient temperature to a digital signal, a memory means for storing data which is provided to said VCO as an optimal external control voltage in response to said ambient temperature, and a digital/analog converter for converting said stored data to an analog signal and outputting said analog signal to said VCO as said optimal external control signal.
According to a third aspect of the present invention, in the first aspect, temperature characteristics of said VCO are measured beforehand.
According to the fourth aspect of the present invention in the second aspect, the data stored in said memory means, which are provided to said VCO as optimal external control voltages, are based on said measured temperature characteristics of said VCO.
According to a fifth aspect of the present invention, in the second aspect, said data stored in said memory means is erasable if necessary.
According to the sixth aspect of the present invention, in the second aspect, said memory means is an electrically erasable programmable read only memory (EEPROM).


REFERENCES:
patent: 5572169 (1996-11-01), Iwamoto
patent: 5892408 (1999-04-01), Binder
patent: 6023197 (2000-02-01), McKinney et al.
patent: 6121844 (2000-09-01), Suzuki
patent: 6121845 (2000-09-01), Eribes
patent: 62-202618 (1987-09-01), None
patent: 2-2721 (1990-01-01),

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