Oscillators – Automatic frequency stabilization using a phase or frequency... – With intermittent comparison controls
Reexamination Certificate
1999-12-03
2001-07-03
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
With intermittent comparison controls
C331S017000, C331S025000, C331S027000, C360S051000
Reexamination Certificate
active
06255911
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a phase locked loop (PLL) circuit, and more particularly, to a PLL circuit that is preferable for use in a disk apparatus.
In addition to data, clock information is recorded on a recording medium, such as a magnetic disk or an optical disk. Clock information is recorded when the recording medium is formatted or when data is written on the recording medium. With reference to
FIG. 1
, clock information c may be recorded on the recording medium when the recording medium is manufactured. A spiral recording track
100
is formed on the recording medium. The clock information c is recorded on the track
100
at equal angular intervals.
A disk apparatus, which reads and writes data on a recording medium, includes a PLL circuit
101
as shown in FIG.
2
. Referring also to
FIG. 1
, the PLL circuit
101
multiplies a reference clock signal RC, which is based on the clock information c read from a recording medium
102
, by a multiplication ratio N to generate a clock signal CLK. The disk apparatus records data on the recording track
100
from one clock information c to the next clock information c in accordance with the clock signal CLK.
However, if the recording surface is scratched for one reason or another or if the recording surface is smudged, the clock information c may be detected at a location differing from its original position or may not even be detected at all.
Referring to FIG.
3
(
a
), when information similar to the clock information c is recorded at a location that differs from the original position, noise X may be included in the reference clock signal RC and thereby shorten the pulse cycle of the reference clock signal RC. Although only a single pulse of the noise X is shown in FIG.
3
(
a
), a plurality of fine noise pulse signals would actually be included in the reference clock signal RC. Referring to FIG.
3
(
b
), when there is missing clock information c, the pulse cycle of the reference clock signal RC at the location Y where the clock information c is missing becomes long. The cycle of a clock signal CLK generated by such an erroneous reference clock signal RC differs from the cycle of an optimal clock signal CLK generated by a normal clock information c. Accordingly, the PLL circuit
101
requires a long length of time to generate an optimal and stable clock signal CLK from the recorded clock information c. Consequently, an error may occur when data is read or written (read/write error) and the time required to access the disk may increase.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a PLL circuit that generates a normal clock signal even if noise is included in the reference clock signal or even if a pulse is missing in the reference clock signal.
To achieve the above object, the present invention provides a PLL circuit including a phase comparator for comparing a phase of a reference signal and a phase of a feedback signal and generating a phase difference signal. A charge pump is connected to the phase comparator to generate an output signal in accordance with the phase difference signal. A low-pass filter is connected to the charge pump for smoothing the charge pump output signal and generating a control voltage signal. A voltage controlled oscillator is connected to the low-pass filter to generate an oscillation output signal having a frequency corresponding to the control voltage signal. A divider is connected to the voltage controlled oscillator to divide the oscillation output signal and generate the feedback signal. A time information generating circuit is connected to the divider to generate time information from the oscillation output signal. The time information indicates a predetermined time period during which a presumed input time of the reference signal is included. A control circuit is connected to the time information generating circuit. The control circuit refers to the time information to permit the output of the oscillation output signal when the reference signal is being input during the predetermined time period and maintain the output of the oscillation output signal, having a predetermined cycle, when the reference signal is not being input during the predetermined time period.
In another aspect of the present invention, a control device of a PLL circuit is provided. The PLL circuit includes a voltage controlled oscillator for comparing the phase of a reference signal and the phase of a feedback signal and generating an oscillation output signal having a frequency corresponding to a control voltage signal. The control device includes a control circuit that refers to time information generated from the oscillation output signal and indicating a predetermined time period during which a presumed input time of the reference signal is included. The control circuit permits the output of the oscillation output signal when the reference signal is input during the predetermined time period and maintains the output of the oscillation output signal, having a predetermined cycle, when the reference signal is not input during the predetermined time period.
In a further aspect of the present invention, a disk apparatus for reproducing data recorded on a recording medium and/or writing data on a recording medium in accordance with an oscillation output signal is provided. The disk apparatus includes a PLL circuit for comparing a phase of a reference signal and a phase of a feedback signal. The PLL circuit includes a voltage controlled oscillator for generating the oscillation output signal having a frequency corresponding to a control voltage signal. The reference signal is generated based on clock information recorded on the recording medium. The disk apparatus further includes a control device of the PLL circuit. The control device has a control circuit that refers to time information generated from the oscillation output signal and indicating a predetermined time period during which a presumed input time of the reference signal is included. The control circuit permits the output of the oscillation output signal when the reference signal is input during the predetermined time period and maintains the output of the oscillation output signal having a predetermined cycle when the reference signal is not input during the predetermined time period.
In a further aspect of the present invention, a method for controlling a PLL circuit of a disk apparatus is provided. The disk apparatus reproduces data recorded on a recording medium and/or writes data on a recording medium in accordance with a clock signal. The PLL circuit compares a phase of a reference signal and a phase of a feedback signal to determine if they match a phase of the clock signal. The method includes the steps of maintaining the output of the clock signal preceding a seek operation when the disk apparatus is performing the seek operation on the recording medium by deactivating the phase matching carried out by the PLL circuit and commencing the phase matching when the seek operation is completed.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4901035 (1990-02-01), Cleveland
patent: 5410572 (1995-04-01), Yoshida
patent: 10134515 (1998-05-01), None
Itakura Akihiro
Niwa Takahiro
Fujitsu Limited
Greer Burns & Crain Ltd.
Grimm Siegfried H.
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