PLL circuit, phase shifting method, and IC chip

Details PLL circuit, phase shifting method, and IC chip PLL circuit, phase shifting method, and IC chip

2007-10-31

2010-06-01

Kinkead, Arnold (Department: 2817)

Demodulators

Phase shift keying or quadrature amplitude demodulator

Input signal combined with local oscillator or carrier...

C329S304000, C329S306000, C329S308000, C332S103000, C455S110000, C375S223000, C375S302000, C375S322000

Reexamination Certificate

active

07728657

ABSTRACT:
A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by Π/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

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Japanese Office Action issued Aug. 12, 2008 for corresponding Japanese Application No. 2006-298815.
Singapore Examination Report; Application No. 200717131-7; Dated Jul. 3, 2008.

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