PLL circuit having reduced capacitor size

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

Reexamination Certificate

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C327S157000

Reexamination Certificate

active

07154345

ABSTRACT:
A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, whereVVCO=xC′⁢ICP2⁢t+ICP2⁢R2VVCO=VCO input voltageIcp2is the current output by the second charge pumpR2=second resistanceC′=new capacitance value=C*XC=original capacitance value.

REFERENCES:
patent: 5384502 (1995-01-01), Volk
patent: 6222421 (2001-04-01), Kiyose
patent: 6538519 (2003-03-01), Lo et al.
patent: 2003/0034846 (2003-02-01), Fan
patent: 10050294 (2002-07-01), None

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