PLL circuit having a phase offset detecting phase comparator

Details PLL circuit having a phase offset detecting phase comparator PLL circuit having a phase offset detecting phase comparator

2001-11-08

2003-04-01

Lee, Benny (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S011000, C331S025000

Reexamination Certificate

active

06542038

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a PLL (Phase Locked Loop) circuit.
As shown in
FIG. 1
, a PLL circuit normally includes a phase comparator
1
, a charge pump
2
, an LPF (Low Pass Filter)
3
, a VCO (Voltage Controlled Oscillator)
4
, and a frequency divider
5
. The charge pump
2
in the PLL circuit turns ON/OFF switches UP, DN between two current sources so as to charge/discharge a pump output node, thereby determining a control voltage to be applied to the VCO
4
. Conventionally, however, turning ON/OFF the switches UP, DN varies a current supplied from the current sources CS
1
, CS
2
, causing variation in control voltage.
A countermeasure against this problem is disclosed in Ian A. Young et al., “A PLL Clock Generator with 5 to 110 MHz Lock Range for Microprocessors”, ISSCC 1992 Digest of Technical Papers, pp. 50-51, February 1992. More specifically, as shown in
FIG. 1
, differential switches UP, DN, UP′, DN′ are provided in the charge pump
2
so that a constant current is continuously supplied from the current sources CS
1
, CS
2
. An amplifier (AMP) circuit is added in order to prevent the control voltage from varying whichever path a current flows through.
This structure achieves significant improvement in terms of the variation in control voltage. However, the offset of the AMP circuit itself causes the phase offset between a reference signal applied to the phase comparator
1
and a comparison signal, i.e., an output of the VCO
4
frequency-divided and fed back to the phase comparator
1
.
Recent increase in operation speed of the PLL circuit causes an increasing demand for a PLL circuit requiring compensation of the phase relation between its input and output, such as a PLL circuit for LVDS (Low Voltage Differential Signaling) or a clock recovery circuit. Accordingly, the phase offset between the reference signal and the comparison signal that are applied to the phase comparator
1
is highly problematic. It is therefore required to find a solution of this problem.
SUMMARY OF THE INVENTION
The present invention is made in view of the foregoing problems, and it is an object of the present invention to provide a PLL circuit capable of easily detecting phase offset and also capable of reliably reducing the phase offset without increasing jitter of an output signal.
In order to achieve the above object, according to one aspect of the invention, a PLL circuit for producing an output signal synchronized with a received reference signal includes: a phase comparator for comparing the reference signal and a comparison signal with each other in terms of a phase; a charge pump for producing a control voltage from an output of the phase comparator; a low pass filter (LPF) for smoothing the control voltage; a voltage controlled oscillator (VCO) for producing an output having a frequency according to the smoothed control voltage; a phase-offset detecting phase comparator for comparing the reference signal and the output of the VCO in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the output of the VCO by the first delay control signal to produce the comparison signal; and a second delay element for adding delay to the output of the VCO by the second delay control signal to produce the output signal.
In order to achieve the above object, according to another aspect of the invention, a PLL circuit for producing an output signal synchronized with a received reference signal includes: a phase comparator for comparing the reference signal and a comparison signal with each other in terms of a phase; a charge pump for producing a control voltage from an output of the phase comparator; a low pass filter (LPF) for smoothing the control voltage; a voltage controlled oscillator (VCO) for producing as the output signal an output having a frequency according to the smoothed control voltage; a frequency divider having a delay control function, for dividing the output of the VCO into the comparison signal; an auxiliary frequency divider having a delay control function, for dividing the output of the VCO into an auxiliary comparison signal in the same manner as that of the frequency divider having the delay control function; and a phase-offset detecting phase comparator for comparing the reference signal and the auxiliary comparison signal with each other in terms of a phase to detect phase offset, and producing a delay control signal corresponding to the phase offset, wherein the frequency divider having the delay control function is structured such that delay is controlled by the delay control signal.


REFERENCES:
patent: 5113152 (1992-05-01), Norimatsu
patent: 5202906 (1993-04-01), Saito et al.
patent: 5281863 (1994-01-01), Bond et al.
patent: 6404291 (2002-06-01), Riley
Ian A. Young, et al, “A PLL Clock Generator with 5 to 110MHz Lock Range for Microprocessors,” Feb., 1992, ISSCC 1992 Digest of Technical Papers, pp. 50-51.

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