PLL circuit for producing a clock signal

Details PLL circuit for producing a clock signal PLL circuit for producing a clock signal

1990-08-23

1991-09-03

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 16, 331 17, 360 7303, H03L 7107, G11B 1928

Patent

active

050458124

ABSTRACT:
A PLL circuit for use in a disk playing apparatus is constructed such that an oscillation output of a VCO is frequency divided at a frequency dividing ratio corresponding to a designated linear velocity in the disk playing apparatus. The frequency divided signal is derived as a reproduction clock signal and a gain of a variable gain amplifier which amplifies a phase error signal and uses the amplified signal as a control voltage of the VCO is changed in accordance with the designated linear velocity, so that a stable loop characteristic is always obtained.

REFERENCES:
patent: 4024464 (1977-05-01), Underhill et al.

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