PLL circuit for generating output signal synchronized with input

Details PLL circuit for generating output signal synchronized with input PLL circuit for generating output signal synchronized with input

1988-11-15

1989-09-26

Isen, Forester W.

Electrical audio signal processing systems and devices

Binaural and stereophonic

Broadcast or multiplex stereo

329316, 329325, 331 25, H04H 500

Patent

active

048706841

ABSTRACT:
A PLL circuit comprises a variable frequency divider (7) for frequency-dividing a signal having a reference frequency f.sub.1 with a frequency dividing ratio n.sub.1 or n.sub.2, a fixed frequency divider (8) for further frequency-dividing an output of the variable frequency divider with a frequency dividing ratio n.sub.0, to generate a first output signal and a second output signal which is out of phase by 90.degree. from the first output signal, multiplier (10) for multiplying an input signal by the second output signal, a comparator (11) for comparing an output of the multiplier with a predetermined reference voltage, and a D-type flip-flop (12) receiving as a D input an output of the comparator and receiving as a clock input the first output signal, an output of the D-type flip-flop (12) being applied to the variable frequency divider (7). When the second output signal leads the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an "L" level, so that the large frequency dividing ratio n.sub.2 is selected. On the other hand, when the second output signal lags the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an "H" level, so that the small frequency dividing ratio n.sub.1 is selected.

REFERENCES:
patent: 4047116 (1977-09-01), Ogita
patent: 4611226 (1986-09-01), Buhse et al.
patent: 4739284 (1988-04-01), McGinn
patent: 4817150 (1989-03-01), Filliman

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