PLL circuit, data detection circuit and disk apparatus

Details PLL circuit, data detection circuit and disk apparatus PLL circuit, data detection circuit and disk apparatus

2001-12-07

2004-09-07

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

C360S032000, C360S039000, C360S065000, C360S031000, C360S055000, C360S027000, C369S047360, C369S047180, C369S059160, C369S059180, C369S059190, C369S059200, C369S059210

Reexamination Certificate

active

06788484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL circuit for generating a clock signal from an input signal, a data detection circuit for identifying and playing back information in an input signal using a PLL circuit, and a disk apparatus such as a magnetic disk apparatus or an optical disk apparatus for playing back information recorded on a magnetic disk or an optical disk using a data detection circuit.
2. Description of the Related Art
Owing to the development of the information technology and the start of ground wave digital broadcasting in recent years and so forth, it is demanded to store and edit a large amount of information including video information. As a storage apparatus for storing such a large amount of information, an optical disk apparatus, a magnetic disk apparatus, a magnetic tape apparatus and like apparatus are used. However, the optical disk apparatus is most superior if editing, random accessing and the durability are taken into consideration. However, an existing DVD (Digital Versatile Disk) apparatus does not have a sufficient capacity for continuous recording of a program of BS (Broadcasting Satellite) digital broadcasting because the DVD has a limited capacity of approximately 5 GB (gigabytes) for one face thereof. Therefore, much effort is directed to investigation for the increase of the capacity of a disk apparatus.
It is a problem to the increase of the recording density of an optical disk and a magnetic disk that, as the recording density increases, the intersymbol interference of the readout signal increases, and this decreases the S/N (signal to noise) ratio of the signal and increases the error rate of the detection information. In order to solve the problem to realize high density recording of the optical disk, decrease of the wavelength of a laser beam, increase of the numerical aperture (NA) and the super-resolution (magnetism, light or medium) are used principally. The techniques just mentioned are directed to decrease of the diameter of a converged beam spot to reduce the influence of the intersymbol interference. Meanwhile, in order to increase the recording density of the magnetic disk, use of a GMR (Giant Magneto-Resistive) head and contact recording are used principally. Also the techniques just mentioned are directed to decrease of the intersymbol interference similarly to those for the optical disk.
The techniques given above, however, have a compatibility problem and an apparatus cost problem. On the other hand, a method of increasing the recording density through PRML (Partial Response Maximum Likelihood) detection which positively utilizes the intersymbol interference has been proposed, and this technique is progressively applied to disk apparatus on the market. Since the technique of increasing the recording density by PRML detection digitally processes a readout signal to raise the detection performance, the compatibility can be assured and also a rise of the cost can be suppressed through application of the LSI technology. The technique is further advantageous in that it can be combined with another technique for increasing the recording density.
The PRML is a detection method which uses PR (Partial Response) a combination of waveform equalization and maximum likelihood detection, and it is well known that the PRML has a high playback performance even from a high density recorded playback waveform having a deteriorated resolution by using maximum likelihood detection based on an intersymbol interference amount of a playback channel. For example, a document
Proc. SPIE
, vol. 2338, pp.314-318 discloses an optical disk to which the PRML is applied. Where the PRML is applied to an optical disk, a readout signal read out from the optical disk is waveform equalized in advance so that it may be a signal of a particular PR channel and is then converted into digital information by an A/D (Analog to Digital) converter of 8 bits or the like. Naturally, digital equalization may be performed after such A/D conversion. Waveform data after such equalization have a correlation to preceding and following sample values and can be represented in a state transition diagram. A maximum likelihood detector has the state transition incorporated therein and, even if the S/N ratio of time series input data is low, can detect information with a low error rate by selecting such time series input data which satisfies the state transition and besides exhibits a minimum error.
To determine a pattern string of a maximum likelihood from all possible combinations on an actual circuit is difficult in terms of the circuit scale and the working speed. Therefore, such determination is usually realized by performing selection of a path step by step using an algorithm called Viterbi algorithm disclosed in a document
IEEE Transaction on Communication
, VOL. COM-19, October 1971. A detector which implements the Viterbi algorithm is called Viterbi detector.
A pulse formation circuit including the PRML detection and digital circuits connected to the pulse formation circuit such as an ECC (Error Correction Code) decoder operate in synchronism with a clock, and therefore, a clock signal is required. Since a readout signal of a disk apparatus has a synchronizing clock signal whose frequency is varied by uneven rotation of the spindle or by a very small inclination of the disk, usually a feedback control circuit called PLL (Phase-Locked Loop) for extracting a variation amount from the readout signal to allow follow-up control is required. Conventionally, the PLL is formed using edge position information of a binary pulse signal obtained by threshold detection of an input waveform with a certain threshold level.
However, as the intersymbol interference of the readout signal increases as the recording density onto a disk increases, a problem appears that jitters (fluctuations in time) of the binary pulse signal increase, resulting in, in the worst case, cancellation of the phase locked state of the PLL. Although a large number of simulation results that have a good detection performance, even when a low resolution an input waveform of a low resolution is obtained by the PRML, have been reported, they are based on the premise that a clock signal can be extracted accurately from within the readout signal. However, when the clock signal includes a lot of jitter or when PLL locking is cancelled, wrong information is outputted. In other words, in high density recording/playback, the detection performance of the detector, e.g., such as a PRML detector, relies much upon the follow-up performance of the PLL.
A PLL circuit which satisfies the request for improvement in PLL follow-up performance is disclosed in Japanese Patent Laid-Open No. 2000-182335 or Japanese Patent Laid-Open No. 172250/1998. The PLL circuit disclosed in Japanese Patent Laid-Open NO. 2000-181335 is shown in FIG.
16
. Referring to
FIG. 16
, the PLL circuit includes an equalizer
101
for converting the waveform of an input signal into a waveform of a desired frequency characteristic, an A/D converter
102
for converting the output signal of the equalizer
101
into a digital signal and outputting the digital signal at a timing of a predetermined clock signal, a phase comparator
103
for extracting phase information of the input signal from the output signal of the A/D converter
102
using a plurality of threshold values set in advance, a loop filter
104
for integrating the phase information outputted from the phase comparator
103
, a voltage controlled oscillator
105
for outputting the predetermined clock signal whose oscillation frequency is controlled in accordance with an output signal of the loop filter
104
, and a maximum likelihood detector
106
for detecting information included in the output signal of the A/D converter
102
.
In short, the PLL circuit disclosed in Japanese Patent Laid-Open No. 2000-182335 generates phase information from a plurality of pieces of threshold detection information generated from a plurality of different threshold val

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