PLL circuit configured to distribute its loop control signal...

Details PLL circuit configured to distribute its loop control signal... PLL circuit configured to distribute its loop control signal...

2007-12-25

2007-12-25

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C375S376000, C327S156000

Reexamination Certificate

active

11357939

ABSTRACT:
A semiconductor integrated circuit includes a phase-locked loop (PLL) circuit configured to generate an oscillation output signal synchronized with a reference clock and a plurality of clock and data recovery (CDR) circuits configured to adjust a phase of the oscillation output signal and a phase of serial data. The PLL circuit converts a voltage output from a loop filter, the voltage functioning to control an oscillation frequency of an oscillator, into a current and delivers the converted current to the plurality of CDR circuits. Therefore, in a case where clock signals used in a plurality of serial transmission channels are synchronized with one another, limitations on layout of clock wiring from the PLL circuit to the CDR circuits and the occurrence of jitter are reduced.

REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 6927611 (2005-08-01), Rhee et al.
patent: 2004/0228636 (2004-11-01), Pathak et al.
patent: 2007/0047689 (2007-03-01), Menolfi et al.
patent: 2007/0058768 (2007-03-01), Werner
patent: 2007/0153950 (2007-07-01), Dosaka
patent: A-11-205133 (1999-07-01), None
patent: A-2000-243939 (2000-09-01), None
patent: A-2004-15032 (2004-01-01), None

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