PLL circuit capable of preventing malfunction of FF circuits con

Details PLL circuit capable of preventing malfunction of FF circuits con PLL circuit capable of preventing malfunction of FF circuits con

1999-01-15

2000-11-14

Le, Dinh T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327149, 327237, 327175, 327172, H03L 706

Patent

active

061475327

ABSTRACT:
A PLL circuit including a delay circuit which delays an output of one of inverters constituting a VCO by an amount designated externally via a delay control circuit. An operational circuit carries out logical operation between the output of the delay circuit and an output of the final stage inverter of the inverters, and outputs a second clock signal whose duty differs from that of a first clock signal output from a buffer circuit. The two clock signals are supplied to flip-flop circuits of different circuit blocks so as to prevent malfunction of these flip-flop circuits.

REFERENCES:
patent: 5087829 (1992-02-01), Ishibashi et al.

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