PLL circuit and wireless device

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S148000, C327S157000

Reexamination Certificate

active

07545187

ABSTRACT:
A PLL circuit according to the present invention includes: a voltage controlled oscillator10;a frequency divider30that divides an oscillation signal of the voltage controlled oscillator10and outputs a divided oscillation signal; a first phase comparator40that outputs a phase difference between the divided oscillation signal of the frequency divider30and a reference signal; a charge pump60that converts the output signal of the first phase comparator40into a signal for controlling the voltage controlled oscillator10;a filter that allows a DC component of the output signal of the charge pump60to pass therethrough and outputs a voltage to the voltage controlled oscillator10;a second phase comparator90that averages the phase difference between the divided oscillation signal of the frequency divider30and the reference signal with respect to time; and a current control circuit100that controls an operating current of the frequency divider30based on the phase difference averaged with respect to time by the second phase comparator90.With this configuration, it is possible to provide a PLL circuit that achieves low power consumption and covers a wide range of oscillation frequencies.

REFERENCES:
patent: 5907253 (1999-05-01), Davis et al.
patent: 6163184 (2000-12-01), Larsson
patent: 6667640 (2003-12-01), Asano
patent: 6829318 (2004-12-01), Kawahara
patent: 7348818 (2008-03-01), Hulfachor et al.
patent: 7496168 (2009-02-01), Leonowich et al.
patent: 2001/0052823 (2001-12-01), Hirano et al.
patent: 3488180 (2003-10-01), None

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