Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2011-03-22
2011-03-22
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S03600C, C331S045000, C331S1170FE, C331S1170FE, C331S17700V
Reexamination Certificate
active
07911281
ABSTRACT:
A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.
REFERENCES:
patent: 7383033 (2008-06-01), Holger
patent: 2006/0238259 (2006-10-01), Metaxakis
patent: 2010/0225366 (2010-09-01), Schnaitter et al.
Helleputte, et al. An Ultra-low-Power Quadrature PLL in 130nm CMOS for Impulse Radio Receivers, IEEE Biomedical Circuits and Systems Conference, 2007, pp. 63-66.
Hoshino Hiroaki
Itakura Tetsuro
Otaka Shoji
Watanabe Osamu
Kabushiki Kaisha Toshiba
Mis David
Turocy & Watson LLP
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