PLL circuit and optical communication reception apparatus

Details PLL circuit and optical communication reception apparatus PLL circuit and optical communication reception apparatus

2001-10-18

2003-04-08

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S017000, C331S018000, C331S025000, C375S375000, C375S376000

Reexamination Certificate

active

06545546

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a PLL (Phase Locked Loop) circuit and an optical communication reception apparatus, and more particularly to a PLL circuit which includes a phase detection circuit and a frequency detection circuit and an optical communication reception apparatus which uses a PLL circuit as a production circuit for a clock signal to be used for retiming processing of received data.
FIG. 14
shows a configuration of a PLL circuit which is used commonly. Referring to
FIG. 14
, the PLL circuit shown includes a phase detection (PD) circuit
101
and a frequency detection (FD) circuit
102
and operates in the following manner.
First, the frequency detection circuit
102
performs phase comparison between an input signal DATA and clock signals (ICLK, QCLK). Then, the frequency of a frequency clock VCOCLK of a voltage-controlled oscillator (VCO)
106
is controlled through a charge pump (CP) circuit
104
and a loop filter
105
based on a result of the comparison to pull the oscillation frequency of the VCO
106
to a target oscillation frequency. The clock signals (ICLK, QCLK) are produced based on the oscillation frequency clock VCOCLK of the VCO
106
by a clock generator
107
.
Then, the phase detection circuit
101
performs phase comparison between the input signal DATA and the oscillation frequency clock VCOCLK of the VCO
106
. Then, the phase detection circuit
101
controls the phase of the frequency clock VCOCLK of the VCO
106
through another charge pump circuit
103
and the loop filter
105
based on a result of the comparison to cause the phase of the frequency clock VCOCLK of the VCO
106
with the phase of the input signal DATA
In a PLL circuit of the type described, a frequency comparison circuit of such a configuration as shown in
FIG. 15
is conventionally used for the frequency detection circuit
102
. In the following, a detailed circuit configuration and operation of the frequency detection circuit
102
are described.
It is assumed here that the digital signal DATA inputted to the frequency detection circuit
102
has a non-return-to-zero (NRZ) waveform. It is also assumed that the clock generator
107
divides the oscillation frequency clock VCOCLK of the VCO
106
to a predetermined dividing ratio 1
(in the example described, n=1) to produce the clock signal ICLK and shifts the phase of the clock signal ICLK by 90 degrees to produce the clock signal QCLK, and the clock signals ICLK and QCLK are inputted to the frequency detection circuit
102
.
First, a data input terminal
111
to which the input signal DATA of an NRZ waveform is linked is connected to the D (data) input terminal of a D-type flip-flop (D-FF)
112
and connected also to an input terminal A of an exclusive OR (EX-OR) gate
113
. Meanwhile, an ICLK input terminal
114
to which the clock signal ICLK is inputted is connected to an input terminal A of each of a pair of AND gates
116
and
117
while a QCLK input terminal
115
to which the clock signal QCLK is inputted is connected to the other input terminals B of the AND gates
116
and
117
. The input terminal A of the AND gate
117
is a negated input terminal through which the clock signal ICLK is inputted with the reversed polarity.
The output terminals of the AND gates
116
and
117
are connected to the D input terminals of D-FFs
118
and
119
, respectively. The output terminal of the EX-OR gate
113
is connected to the CLK input terminals of the D-FFs
118
and
119
. The Q output terminals of the D-FFs
118
and
119
are connected to the D input terminals of D-FFs
120
and
121
, and the Q output terminals of the D-FFs
120
and
121
are connected to the D input terminals of D-FFs
122
and
123
, respectively. The CLK terminals of the D-FF
112
and the D-FFs
120
to
123
are connected to the ICLK input terminal
114
.
The Q output terminal of the D-FF
122
is connected to an input terminal A of an AND gate
124
. The Q output terminal of the D-FF
123
is connected to an input terminal B of another AND gate
125
. The Q output terminal of the D-FF
120
is further connected to an input terminal A of the AND gate
125
, and the Q output terminal of the D-FF
121
is connected to an input terminal B of the AND gate
124
. The output terminals of the AND gates
124
and
125
are connected to circuit output terminals
126
and
127
, respectively.
A DOWN pulse signal for controlling the VCO
106
of
FIG. 14
to lower the oscillation frequency of it is extracted as an output signal from the AND gate
124
while an UP pulse signal for controlling the VCO
106
to raise the oscillation frequency is extracted as an output signal from the AND gate
125
. The DOWN pulse signal and the UP pulse signal are supplied to the charge pump circuit
104
of FIG.
14
through the circuit output terminals
126
and
127
, respectively.
Now, circuit operation of the frequency detection circuit having the configuration described above is described with reference to a timing chart of FIG.
16
. In
FIG. 16
, waveforms (a) to (o) indicate waveforms at nodes (a) to (o) of
FIG. 15
, respectively.
First, the clock signal ICLK (a) has a pulse waveform wherein it rises to the “H” (high) level at time t
0
and falls to the “L” (low) level at time t
2
. Similarly, the clock signal ICLK (a) rises at times t
4
, t
8
, t
12
, . . . and falls at times t
6
, t
10
, . . . The clock signal ICLK (a) is supplied to the input terminals A of the AND gates
116
and
117
through the ICLK input terminal
114
and supplied also to the CLK terminals of the D-FF
112
and the D-FFs
120
to
123
.
The clock signal QCLK (b) has a pulse waveform having a phase shifted by 90 degrees, more particularly, delayed by 90 degrees with respect to the clock signal ICLK (a). In particular, the clock signal QCLK (b) rises to the “H” level at times t
1
, t
5
, t
9
, . . . and falls to the “L” level at times t
3
, t
7
, t
11
, . . . The clock signal QCLK (b) is supplied to the input terminals B of the AND gates
116
and
117
.
The AND gate
116
logically ANDs the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (c) of the AND gate
116
exhibits the “H” level within those periods within which both of the clock signals ICLK and QCLK have the “H” level, that is, within the period from time t
1
to time t
2
, the period from time t
5
to time t
6
and the period from time t
9
to time t
10
. Within the other periods, that is, within the period from time t
0
to time t
1
, the period from time t
2
to time t
5
, the period from time t
6
to time t
9
and the period from time t
10
to time t
12
, the output signal (c) of the AND gate
116
exhibits the “L” level.
Meanwhile, the AND gate
117
logically ANDs the inverted clock signal ICLKX of the clock signal ICLK (a) and the clock signal QCLK (b). Therefore, the output signal (d) of the AND gate
117
exhibits the “H” level within those periods within which both of the clock signals ICLKX and QCLK have the “H” level, that is, within the period from time t
2
to time t
3
, the period from time t
6
to time t
7
and the period from time t
10
to time t
11
. Within the other periods, that is, within the period from time t
0
to time t
2
, the period from time t
3
to time t
6
, the period from time t
7
to time t
10
and the period later than time t
11
, the output signal (d) of the AND gate
117
exhibits the “L” level.
In the timing chart of
FIG. 16
, the period within which the output signal (c) exhibits the “H” level is represented as a period A while the period within which the output signal (d) exhibits the “H” level is represented as a period B.
Meanwhile, the NRZ input signal DATA (f) is supplied immediately to the input terminal A of the EX-OR gate
113
through the data input terminal
111
and supplied also to the D input terminal of the D-FF
112
. The D-FF
112
fetches the “H” level “L” level of the input waveform to the D input terminal at the timing of a rising edge of the clock signal ICLK (a). In this instance, if the input signal DA

Affiliated with

Also associated with

Rating

PLL circuit and optical communication reception apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL circuit and optical communication reception apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL circuit and optical communication reception apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3093074