PLL circuit and method of controlling the same

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S157000

Reexamination Certificate

active

07920000

ABSTRACT:
A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability.

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patent: 2010/0134157 (2010-06-01), Kawashima
patent: 2001-520471 (2001-10-01), None
patent: 2002-208857 (2002-07-01), None
patent: 2005-143030 (2005-06-01), None

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