Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2003-05-02
2004-12-28
Pascal, Robert (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S017000, C327S156000
Reexamination Certificate
active
06836188
ABSTRACT:
RELATED APPLICATION
Under 35 USC §119, this application claims the benefit of a foreign priority application filed in Germany, serial number 102 19 857.8, filed May 3, 2002.
FIELD OF THE INVENTION
The invention relates to a PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, in particular the self-jitter in a signal which is emitted by a clock and data recovery circuit (CDR) within a receiver.
BACKGROUND OF THE INVENTION
FIG. 1
shows an ADPLL circuit (ADPLL: All Digital Phase Locked Loop) according to the prior art. PLL circuits may be either analog or digital. PLL circuits are phase locked loops and are used for synchronizing the frequency and phase of two oscillations. In this case, PLL circuits essentially comprise a phase comparison circuit for producing a phase difference signal and which determines the phase difference between a received signal and a fed-back output signal from the PLL circuit, a downstream loop filter for filtering the phase difference signal that is produced, and an oscillator which is controlled by the filtered phase difference and generates the output signal from the PLL circuit.
FIG. 2
a
shows a digital loop filter according to the prior art (P-regulator), which is used within a conventional ADPLL circuit, as is illustrated in FIG.
1
.
FIG. 2
b
shows the associated transmission characteristic of the conventional digital loop filter (P-regulator) as illustrated in
FIG. 2
a.
PLL circuits are circuits in which a frequency is synchronized by means of a reference frequency until the output signal and the reference signal match in frequency and phase. The received signal is generally a reference clock signal. If the reference clock signal is obtained by means of a clock and data recovery circuit CDR (Clock Data Recovery) within a receiver, the received signal is subject to jitter which is formed from the self-jitter of the clock and data recovery circuit CDR and from data jitter.
A conventional PLL circuit having the loop jitter illustrated in
FIG. 2
is used for stabilizing the applied reference clock signal. A conventional PLL circuit, as is illustrated in
FIG. 1
, acts like a low-pass filter in which high-frequency signal components are filtered out and low-frequency signal components of the applied reference clock signal are passed on. In consequence, the PLL circuit suppresses high-frequency signal interference, but the reference clock signal may diverge slowly if the frequency of the reference clock signal changes.
The conventional PLL circuit according to the prior art, as is illustrated in
FIG. 1
, contains a linear P-regulator and a linear loop filter, as is shown in
FIG. 2
a
. The linear transfer function of the digital loop filter, as is shown in
FIG. 2
b
, means that the signal components of the self-jitter of the received signal are amplified in accordance with the gain factor k setting, as is illustrated in
FIG. 6
a
. The self-jitter which is produced by the clock and data recovery circuit CDR is amplified in accordance with the gain factor k setting of the digital loop filter. The higher the gain factor k setting, the higher is the gain of the self-jitter signal component as well. If the gain factor k of the linear P-regulator, as is illustrated in
FIG. 2
a
, is set to be small, although this reduces the gain of the self-jitter in the same way, the ADPLL circuit will no longer be able to follow the reference clock signal that is emitted by the clock and data recovery circuit CDR if the gain factor k setting is too low. In this case, the frequency of the clock signal which is stabilized by the PLL circuit drifts away from the frequency of the received data signal, and data losses can occur when transferring the received data to a data register which is clocked by the stabilized clock signal.
SUMMARY OF THE INVENTION
The object of the present invention is therefore to provide a PLL circuit which is able to completely eliminate the self-jitter in a signal which is received by a control circuit, and which can follow a frequency change in the received signal.
The invention provides a PLL circuit for eliminating self-jitter in a signal which is received by a control circuit, having a phase comparison circuit for producing a phase difference signal, which indicates the phase difference between the received signal and a fed-back output signal from the PLL circuit, a loop filter for filtering the phase difference signal which is produced, an oscillator, which is controlled by the filtered phase difference signal, for producing the output signal from the PLL circuit, with the loop filter having a nonlinear transfer function.
In one preferred embodiment of the PLL circuit, the transfer function is point-symmetrical about the zero point.
This offers the advantage that the self-jitter, which likewise occurs symmetrically with respect to the zero point, is eliminated completely in both phase difference amplitude directions.
In one particularly preferred embodiment of the PLL circuit according to the invention, the nonlinear transfer function of the loop filter has three transmission ranges with the loop filter in a first transmission range having a signal gain of zero for a small phase difference up to a first threshold value, with the loop filter having a nonlinear signal gain in a second transmission range for a medium phase difference between the first threshold value and a second threshold value, and with the loop filter having a constant maximum signal amplitude in a third transmission range for a large phase difference, which is greater than the second threshold value.
The loop filter is preferably digital.
In one particularly preferred embodiment of the PLL circuit according to the invention, the digital loop filter comprises a coefficient memory for storing signal gain coefficients and has a multiplexer which is controlled by the phase difference signal and passes on the stored signal gain coefficients to a multiplier, which multiplies the phase difference signal by the signal gain coefficient that is passed on.
The coefficient memory for the digital loop filter according to the invention is preferably programmable.
In an alternative embodiment of the PLL circuit according to the invention, the loop filter is analog.
The control circuit is preferably a circuit for clock and data recovery within a receiver, with the recovered clock signal being applied to the phase comparison circuit.
The invention furthermore provides a method for eliminating self-jitter in a signal which is received by a control circuit, having the following steps, namely:calculation of the phase difference between the phase of the signal which is received by the control circuit and a nominal phase, amplification of the signal which is received by the control circuit, with the received signal being amplified in a nonlinear manner as a function of the calculated phase difference.
In one preferred embodiment of the method according to the invention for eliminating self-jitter in a signal which is received by a control circuit, the calculated phase difference is compared with programmable phase difference threshold values, with the signal which is received by the control circuit being amplified with a signal gain factor of zero in a first transmission range for a small phase difference up to a first phase difference threshold value, with the signal which is received by the control circuit being amplified in a nonlinear manner by programmable signal gain factors as a function of the calculated phase difference in a second transmission range for a medium phase difference between the first phase difference threshold value and a second phase difference threshold value, and with the signal which is received by the control circuit being output with a constant maximum signal amplitude in a third transmission range for a large phase difference which is greater than the phase difference second threshold value.
The method according to the invention is preferably carried out by means of a signal processor.
The signal processor is preferab
Bonhaus Jorg
Duda Thomas
Chang Joseph
Fish & Richardson P.C.
Pascal Robert
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