PLL circuit and digital signal reproducing apparatus

Details PLL circuit and digital signal reproducing apparatus PLL circuit and digital signal reproducing apparatus

1996-09-30

1998-06-16

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327147, 327553, 331 17, H03L 7093

Patent

active

057677140

ABSTRACT:
A PLL circuit which is used as a reproducing clock forming circuit of a digital signal reproducing apparatus. The PLL circuit is strong against noises and has stable characteristics. Comparison outputs of a phase comparator 3 are outputted in a form of balance (differential) signals and are supplied to a loop filer 4. Output signals of the loop filter 4 are supplied to control voltage input terminals of a VCO 5 in a form of the balance signals. In-phase components of the noises included in control voltages can be cancelled. Time constants of the loop filter can be switched by bipolar transistors Tr31 and Tr32. A balance of the balance signals is not broken by base currents of the transistors Tr31 and Tr32.

REFERENCES:
patent: 3694776 (1972-09-01), Linder
patent: 5144156 (1992-09-01), Kawasaki
patent: 5382838 (1995-01-01), Sasaki et al.
patent: 5499392 (1996-03-01), Grunwell
patent: 5570398 (1996-10-01), Smith
Cox et al., "Phase-locked oscillator initialization", IBM Technical Disclosure Bulletin, vol. 14, No. 14, p. 1222, Sep. 1971.

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