PLL circuit and design method thereof

Details PLL circuit and design method thereof PLL circuit and design method thereof

2005-05-12

2009-06-23

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

07551010

ABSTRACT:
A PLL circuit has an averaging device for averaging a rectangular wave signal output from a phase comparator at every period of a reference clock signal, and for outputting the average value. After the establishment of the phase synchronization of the PLL circuit, the average value of the averaging device becomes a stationary reference level. Accordingly, the output clock signal generated by a voltage controlled oscillator can reduce its output frequency fluctuations in accordance with the reference level.

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U.S. Appl. No. 11/817,502, filed Aug. 31, 2007, Fujiwara.

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