Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-05-31
2001-12-11
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000
Reexamination Certificate
active
06329853
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit and, more specifically, relates to a PLL circuit which permits to restore quickly to a target frequency to be locked when a device concerned enters into an operable condition either after making a power source or after being released from a stand-by condition or a sleep condition thereof.
2. Background Art
In a variety of electronic devices such as visual devices, audio devices and telecommunication devices including recent recording and reproducing devices, a timing clock which serves as a timing reference is used for signal processings such as signal demodulation, signal transmission, signal detection, synchronous detection and synchronous separation. In order to generate the timing clock a PLL circuit is used. Further, such PLL circuit is frequency used for generating a main clock for a system concerned.
In the variety of devices as referred to above, when an operation thereof is not required or the device is not used, a controller therein such as for a CPU and an MPU is usually placed in a stand-by condition or a sleep condition so as to save power consumption. In accordance therewith the PLL circuit is also placed such as in a stand-by condition and a sleep condition.
Further, for a variety of portable electronic devices such as PHSs and portable telephones which require key operations, it is required to immediately enter into an operable condition after a power source is made, therefore, the time interval between the making and the subsequent key operation is short. Thus, PLL circuits for these kinds of electronic devices are required to quickly restore to a target frequency to be locked after the device concerned enters into an operable condition.
Accordingly, in order that a PLL circuit restores a target frequency to be locked in a short time either after a power source thereof being made or after being released from a stand-by condition or a sleep condition and in order that the PLL circuit generates clocks of stable frequency, conventionally, a boosting-up circuit is frequently provided. Such boosting-up circuit is usually designed to operate to rapidly increase a control voltage of a VCO (Voltage Controlled Oscillator Circuit) incorporated in the PLL circuit toward a control voltage (target voltage) of a locked frequency. The boosting-up circuit turns off and terminates its operation at the moment when the control voltage reaches the target voltage.
FIG.
4
(
a
) and
4
(
b
) are diagrams for explaining a characteristic until the control voltage of the VCO incorporated in a PLL circuit how the target frequency are restored, when the PLL circuit is activated. Wherein the abscissa represents an input voltage (control voltage) of the VCO and Vob is a target voltage, and the ordinate represents time t.
FIG.
4
(
a
) represents a case where no boosting-up circuit is provided and it is observed that the PLL circuit is required a comparatively long time to restore to a stable locked frequency either after the power source for the device concerned is made or after being released from a stand-by condition or a sleep condition thereof. Further, the control voltage of the VCO corresponds to the oscillation frequency of the PLL circuit.
FIG.
4
(
b
) represents a characteristic of a conventional PLL circuit which is provided with a boosting-up circuit, in this PLL circuit, because the control voltage is rapidly increased toward the target voltage Vob either after the device concerned is made or after being released from a stand-by condition or a sleep condition thereof, an overshooting and an under shooting are generated in the oscillation frequency of the PLL circuit, in that a so called indicial response characteristic appears. For this reason, a ringing in the oscillation frequency is generated, therefore, it takes a certain time until this characteristic settles. Further, t
1
in the drawing indicates the timing when the boosting-up circuit is turned OFF.
SUMMARY OF THE INVENTION
An object of the present invention is to solve such conventional problems and to provide a PLL circuit which permits to restore quickly to a target frequency to be locked when a device concerned enters into an operable condition either after a power source thereof is made or after a stand-by condition or a sleep condition thereof has been released.
A PLL circuit according to the present invention which achieves the above object, is characterized in that the PLL circuit comprises, a voltage controlled oscillation circuit (VCO), a phase comparing circuit which receives a clock from outside of the PLL circuit and compares phases of an output signal of the voltage controlled oscillation circuit (VCO) and the clock received, an oscillation circuit by means of a PLL loop which generates a control voltage for the voltage controlled oscillation circuit depending on a phase comparison result of the phase comparing circuit and generates the output signal of a specified frequency which is locked to the frequency of the clock; and a boosting-up circuit which receives the clock and the output signal, applies to the PLL loop or causes the PLL loop to generate a signal which causes to shift the control voltage in the direction of oscillating at the specified frequency in response to when the frequency of the output signal assumes a lower limit value or less than that of a predetermined range including the specified frequency with respect thereto and further causes to shift the control voltage in the direction of oscillating at the specified frequency in response to when the frequency of the output signal assumes an upper limit value or more than that of the predetermined range and interrupts activation for the PLL loop when the specific frequency is in the predetermined range, whereby a ringing of the frequency of the output signal which is caused when the PLL circuit is started, is suppressed.
As has been explained above, in the present invention, with respect to the specific oscillation frequency representing the target frequency of the oscillation circuit in the PLL loop the lower limit value and the upper limit value are set in advance in the predetermined range including the specified oscillation frequency, and applies to the PLL loop or causes the PLL loop to generate the signal which causes to shift the control voltage in the direction of oscillating at the specified frequency in response to when the frequency of the output signal assumes a lower limit value or less than that of a predetermined range including the specified frequency with respect thereto and further causes to shift the control voltage in the direction of oscillating at the specified frequency in response to when the frequency of the output signal assumes an upper limit value or more than that of the predetermined range.
The predetermined range to be suppressed is set smaller than a variation range from first upper side to the first lower side of the ringing in the oscillation frequency which varies up and down until the same is locked to the oscillation frequency of the VCO. Further, when the oscillation frequency falls within the range defined by the upper and lower limits, the boost-up circuit is placed in a condition with no activation for the oscillation circuit in the PLL circuit. Thereby, the oscillation circuit in the PLL circuit can be shifted into a stable locked condition under a self loop operation with respect to the frequency of the clock supplied from an outside.
In the present invention a large value of control current which is generated by the boosting-up circuit can be used, therefore, even if a control current having a large value is flown in the PLL oscillation circuit, since the up and down oscillation frequency range of the PLL circuit with respect to the target frequency after the power source of the device concerned is made or after the stand-by condition or the sleep condition thereof is released is restricted by the upper limit frequency and the lower limit frequency, the same is restricted smal
Le Dinh T.
Mattingly Stanger & Malur, P.C.
Rohm & Co., Ltd.
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