PLL circuit

Details PLL circuit PLL circuit

2007-09-13

2009-06-09

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A, C331S008000, C331S025000

Reexamination Certificate

active

07545223

ABSTRACT:
A PLL circuit according to an embodiment of the present invention includes: a phase comparator to output an up signal and a down signal based on a phase difference between a reference clock signal and a feedback clock signal; an offset correcting circuit to correct a pulse width of at least one of the up signal and the down signal to output a modified up signal and a modified down signal; a first charge pump circuit to increase or decrease a charge pump output voltage to be output in accordance with the modified up signal and the modified down signal; a loop filter to filter out noise of the charge pump output voltage and generate a filter voltage; and a voltage-controlled oscillation circuit having an oscillation frequency controlled based on a voltage value of the filter voltage and outputting an output clock signal.

REFERENCES:
patent: 6903585 (2005-06-01), Keaveney
patent: 2006/0119405 (2006-06-01), Kobayashi
patent: 2005-123944 (2005-05-01), None

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