PLL circuit

Details PLL circuit PLL circuit

2002-03-27

2003-10-28

Cunningham, Terry D. (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S025000, C331S00100A, C327S156000

Reexamination Certificate

active

06639475

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to PLL (Phase-Locked Loop) technology. In particular, this invention pertains to a type of PLL circuit that can remove the ripple component from the output signal for the PLL circuit of a fractional frequency division system.
BACKGROUND OF THE INVENTION
A cellular phone is a multiple frequency channel access system. In order to shift the frequency in use to an idle channel, a PLL circuit that allows high-speed lockup is needed.
In
FIG. 5
,
101
represents a PLL circuit with a fractional frequency division system, prior art for the PLL circuit.
This PLL circuit
101
is placed in a semiconductor integrated circuit device that forms the transceiver of a cellular phone. It is composed of oscillator
131
, frequency divider
132
, reference signal generator
133
, phase comparator
134
, charge pump circuit
135
, low-pass filter
136
, controller
138
and compensating circuit
137
.
Oscillator
131
generates an oscillation signal at a frequency corresponding to the signal output from low-pass filter
136
, and outputs the oscillation signal to the output terminal. The oscillation signal is output as external output signal OUT to both frequency divider
132
and to the other circuits in the semiconductor integrated circuit device where PLL circuit
101
is arranged.
Frequency divider
132
performs frequency division for the oscillation signal input to it from oscillator
131
, generates comparison signal V, and outputs it to phase comparator
134
. Also, reference signal generator
133
outputs reference signal R at a prescribed frequency to phase comparator
134
.
As illustrated by the timing chart shown in
FIG. 6
, phase comparator
134
rises in synchronization with the rise of comparative signal V and reference signal R, respectively, and, when reference signal R falls, it outputs output signals D and U in synchronization with the fall of reference signal R.
Output signals U and D of phase comparator
134
are output to charge pump circuit
135
.
FIG. 9
is a diagram illustrating the constitution of charge pump circuit
135
. This charge pump circuit
135
has output terminal
185
, source-side constant current circuit
171
, sink-side constant current pump circuit
172
, source-side switch circuit
181
, and sink-side switch circuit
182
.
When phase comparator
134
outputs output signals U and D, respectively, output signals U and D are input to source-side switch circuit
181
and sink-side switch circuit
182
, respectively.
Source-side switch circuit
181
and sink-side switch circuit
182
have upper and lower operation transistors
175
and
177
, upper and lower stand-by transistors
174
,
176
, and inverters
178
and
179
, respectively.
Stand-by transistors
174
and
176
and operation transistors
175
and
177
are all MOS transistors. Stand-by transistor
174
and operation transistor
175
that form source-side switch circuit
181
have their source terminals connected to each other. Similarly, stand-by transistor
176
and operation transistor
177
of sink-side switch circuit
182
are also connected to each other.
The common connection portions of stand-by transistors
174
,
176
with operation transistors
175
,
177
are respectively connected to source-side constant current circuit
171
and sink-side constant current circuit
172
.
The gate terminal of upper stand-by transistor
174
and the gate terminal of lower operation transistor
177
are directly connected to the two output terminals of phase comparator
134
, respectively, and output signals U and D are input as is. On the other hand, the gate terminal of upper operation transistor
175
and the gate terminal of lower stand-by transistor
176
are connected through inverters
178
and
179
to the two output terminals of phase comparator
134
, respectively, and the inverted signals of output signals U and D are input. The constitution is such that for stand-by transistors
174
,
176
and operation transistors
175
,
177
of source-side switch circuit
181
and sink-side switch circuit
182
, when one side is ON, the other side is OFF.
Suppose lower operation transistor
177
is ON, while upper operation transistor
175
is OFF. In this state, only sink-side constant current circuit
172
is connected to output terminal
185
, and constant current CD generated by sink-side constant current circuit
172
(hereinafter referred to as sink-side constant current) is sunk at output terminal
185
.
Suppose upper operation transistor
175
is ON, while lower operation transistor
177
is OFF. In this state, constant current CU generated by source-side constant current circuit
171
(hereinafter referred to as source-side constant current) is output from output terminal
185
.
When output signals U and D are both in “L” state, “L” is input to the gate terminal of upper stand-by transistor
174
, and “H” that is obtained by inversion using inverter
178
is input to the gate terminal of upper operation transistor
175
. Because both upper operation transistor
175
and upper stand-by transistor
174
are P-channel MOS transistors, upper operation transistor
175
is OFF, while upper stand-by transistor
174
is ON, and constant current CU supplied by source-side constant current circuit
171
flows through upper stand-by transistor
174
to ground potential.
On the other hand, “H” that is obtained by inversion using inverter
179
is input to the gate terminal of lower stand-by transistor
176
, and “L” is input to the gate terminal of lower operation transistor
177
. Because both lower stand-by transistor
176
and lower operation transistor
177
are N-channel MOS transistors, lower operation transistor
177
is OFF, while lower stand-by transistor
176
is ON, and constant current CD supplied by sink-side constant current circuit
172
flows through lower stand-by transistor
176
at ground potential. Consequently, constant currents CU and CD do not flow at output terminal
185
.
In this state, when output signals U and D are inverted from “L” to “H,” stand-by transistors
174
and
176
are turned OFF, and, at the same time, operation transistors
175
and
177
are turned ON.
Output signals U and D rise independently in synchronization with the rise of reference signal R and comparison signal V of the preceding stage, respectively. When upper operation transistor
175
alone is ON, source-side constant current CU is output from output terminal
185
, lower operation transistor
177
alone is ON, and sink-side constant current CD is sunk at output terminal
185
. Also, because the magnitudes of the current supply of source-side constant current source
171
and sink-side constant current source
172
are equal to each other, and the current values of constant currents CU and CD are nearly equal to each other, when operation transistors
175
and
177
are ON at the same time, no current flows at output terminal
185
.
Then, when reference signal R falls from “H” to “L,” output signals D and U fall at the same time, so that operation transistors
175
and
177
are turned OFF at the same time, and, as shown in the timing chart of
FIG. 6
, the supply of constant currents CU and CD is always terminated at the same time t
s
.
As explained above, after output signals U and D are converted from “L” to “H,” respectively, during the period of conversion from “L” to “H,” only one of constant currents CU and CD, output, respectively, from source-side constant current source
171
and sink-side constant current source
172
, flows at the output terminal of charge pump circuit
135
. This current is represented by SS in FIG.
6
.
This current SS is output to low-pass filter
136
. Low-pass filter
136
outputs said current SS to oscillator
131
after removing its high-frequency component.
The frequency of the oscillation signal of oscillator
131
is changed in correspondence with the voltage value output from low-pass filter
136
. Said oscillator
131
, frequency divider
132
, reference signal generator
133
, phase comparator
134
, charge pump circ

Affiliated with

Also associated with

Rating

PLL circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with PLL circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and PLL circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3145157