PLL circuit

Details PLL circuit PLL circuit

2000-12-28

2002-08-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000

Reexamination Certificate

active

06441661

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a PLL (Phase-Locked Loop) circuit, and in particular, to a PLL circuit that can reduce the number of false locks than a conventional PLL circuit for a signal that is read from a storage medium such as an MO disk (Magneto-Optical disk), a CD (Compact Disk), an MD (Mini Disk), and HD (Hard Disk), and further can perform locking (synchronizing) operation faster than before.
BACKGROUND ART
A decoding apparatus configured by including a conventional PLL circuit will be described with reference to FIG.
10
.
This decoding apparatus comprises a gain controller
10
receiving a read signal from an MO, a CD, an MD, an HD, or the like as an input signal and performing desired amplifying operation for this input signal, an equalizing filter
20
filtering an output of this gain controller
10
,. a PLL circuit
100
, and a Viterbi decoding circuit
80
outputting a Viterbi decoding result.
The PLL circuit
100
, as shown in
FIG. 10
, comprises an A/D converter
30
performing the A/D conversion of an output of the equalizing filter
20
, a phase difference calculating unit
40
obtaining phase difference on the basis of an output from this A/D converter
30
, a D/A converter
50
for performing the D/A conversion of this phase difference and outputting it, a loop filter
60
for integrating an output of the D/A converter
50
, and a VCO (Voltage Controlled Oscillator)
70
for generating a sampling clock according to an integrated signal.
Each component of this PLL circuit
100
configures a PLL loop as a whole, and by this PLL loop, phase pulling-in operation is performed so that phase difference obtained in the phase difference calculating unit
40
becomes “zero”. In addition, the sampling operation of the A/D converter
30
is performed with synchronizing with the sampling clock from the VCO
70
.
Next, the operation of the PLL circuit
100
having such configuration will be described with reference to drawings.
When an analog signal shown in FIG.
11
(
a
) is given, the A/D converter
30
generates sampled values by sampling the analog signal as well as synchronizing with the rise of the sampling clock from VCO
70
that is shown in FIG.
11
(
b
), and outputs this sampled values. A round mark in FIG.
11
(
a
) shows a sampling point, and its numeric value shows a concrete sampled value. The phase difference calculating unit
40
obtains phase difference between the above-described input analog signal and sampling clock from the next formula (1) on the basis of four sampled values obtained as described above.
Phase difference={Smpl+(−+)−Smpl+(+−)}+{Smpl−(−+)−Smpl−(+−)}  formula (1)
Here, in formula (1), Smpl+(−+) is a positive sampled value when digital sampling values change from a negative (−) to a positive (+), Smpl+(+−) is a positive sampled value when sampled values change from a positive to a negative, Smpl−(−+) is a negative sampled value when sampled values change from a negative to a positive, and Smpl−(+−) is a negative sampled value when sampled values change from a positive to a negative.
The phase difference calculating unit
40
obtains phase difference by formula (1) by using this new value whenever newly taking two sampled values in, and updates a value of the phase difference in turn. This phase difference obtained is digital-analog converted by the D/A converter
50
, and is integrated by the loop filter
60
, this integrated signal becomes a control signal for the VCO
70
, and by this control signal, an oscillation frequency of the VCO
70
is controlled at any time.
At this time, if the relation between the input analog signal in A/D converter
30
and the sampling clock from the VCO
70
is as shown in
FIG. 11
, phase difference by formula (1) becomes “zero”, and hence sampling operation with the sampling clock is performed accurately.
On the other hand, if the relation between the input analog signal and sampling clock is as shown in
FIG. 12
, with obtaining phase difference by formula (1) by using sampled values in the drawing, the phase difference becomes a positive value as phase difference=(7−3)+(−3−(−7))=8, and hence the sample timing of the input analog signal is in a late condition. Thus, feedback operation that advances a phase of the sampling clock is performed.
In addition, if the relation between the input analog signal and sampling clock is as shown in
FIG. 13
, with obtaining phase difference by formula (1) by using sampled values in the drawing, the phase difference becomes a negative value as phase difference=(3−7)+(−7−(−3))=−8, and hence the sample timing of the input analog signal is in an advanced condition. Thus, feedback operation that delays a phase of the sampling clock is performed. If such a feedback control is performed, feedback is performed so that a value of phase difference in formula (1) finally becomes zero, thereby completing pulling-in operation, and performing locking operation.
By the way, as a conventional synchronization method that is different from the above-described one, for example, a method is proposed, the method generating a sampling clock so that edges of the sampling clock correspond to zero-cross points (points where a signal becomes zero) of the input analog signal shown in FIG.
11
(
a
). Nevertheless, in this synchronization method, it becomes necessary to adopt an edge-pulling-in type PLL circuit instead of the PLL loop shown in
FIG. 10
, and to further use other circuit elements such as a delay element. This type of PLL circuit is called an analog type PLL, which cannot perform precise pulling-in operation if the phase pulling-in operation is necessary for data after digital conversion of a signal like a PRML (Partial Response Maximum Likelihood) method.
Furthermore, there is a method of providing two groups of PLL loops each including the A/D converter
50
, loop filter
60
and VCO
70
, which are shown in
FIG. 10
, for accelerating phase (including a frequency) pulling-in speed, one PLL loop of which has a gain that is as high as possible at the time of pulling-in, and another PLL loop of which has a gain that is set low for stabilizing the loop as much as possible after pulling-in.
However, in the conventional PLL circuits, false lock
10
explained below occurs, and hence the performance of the PLL circuits deteriorates remarkably.
What is shown in
FIG. 14
is a case that a frequency of the input signal is a desired value but sampling points are not at desired positions and Smpl−(+−) and Smpl−(−+) correspond to the same sampling point, and hence the operation result of formula (1) becomes “zero”, and the phase difference becomes “zero”. In this case, a state of feedback control by a PLL loop unintentionally becomes stable at a state that the feedback control should not be essentially stable, and hence the false lock (the first false lock) occurs.
A situation which is the same as this will be explained more concretely with reference to FIG.
15
. If sampling points of the input signal become as shown in
FIG. 15
, it is only judged in the conventional technology that sampling points are before or after zero cross, and sampled values are assigned to respective term of formula (1). Owing to this, the phase difference obtained by formula (1) from concrete numeric values shown in
FIG. 15
(sampled values) is Phase difference=(C−A)+(B−B)=(2−2)+(−6−(−6))=0. In this manner, if the phase difference becomes “zero”, feedback control by the PLL loop becomes not effective, and hence there is a possibility that the feedback control becomes stable in a wrong phase.
In addition, what is shown in
FIG. 16
is false lock occurring when frequencies of the sampling clock from the VCO

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