PLD hardwire programming with multiple functional modes

Details PLD hardwire programming with multiple functional modes PLD hardwire programming with multiple functional modes

2006-08-29

2006-08-29

Tan, Vibol (Department: 2819)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C326S040000

Reexamination Certificate

active

07099227

ABSTRACT:
A configuration control circuit (400) allows a PLD to be quickly re-configured to implement different functions without requiring any configuration memory cells. The control circuit (400) includes a first input (IN1) connected to a first hardwired configuration bit (HCB1), a second input (IN2) connected to a second hardwired configuration bit (HCB2), an output (OUT) connected to one or more of the PLD's configurable elements (110), and a select circuit (402) to selectively connect either the first input (IN1) or the second input (IN2) to the output (OUT) in response to a select signal (SEL).

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Xilinx, Inc., “Hardwire Data Book,” 1997, pp. 1-1 to 1-5 and 2-1 to 2-12, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Xilinx, Inc., “The Programmable Logic Data Book,” 1998, pp. 4-1 to 4-40, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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