Playback clock signal generating circuit which uses a first and

Details Playback clock signal generating circuit which uses a first and Playback clock signal generating circuit which uses a first and

1994-06-14

1996-11-26

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

G11B 509

Patent

active

055791840

ABSTRACT:
A playback clock signal generating circuit has first and second phase-locked loops PLLs. The first PLL has a voltage-controlled oscillator VCO controllable by an output signal from a low-pass filter for outputting a signal, a variable frequency divider for varying a frequency-dividing number depending on head position information and frequency-dividing the signal from the VCO with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to a predetermined frequency step, a phase comparator for detecting the phase or frequency difference between an output signal from the variable frequency divider and the reference signal, and outputting the detected phase or frequency difference to the low-pass filter. The second PLL has a VCO controllable by a low-pass filter for outputting a signal, a mixer for frequency-converting the signal from the VCO with the signal from the VCO of the first PLL to output a playback clock signal, and a phase comparator for detecting the phase difference between a reproduced data signal and the playback clock signal and outputting the detected phase difference to the low-pass filter.

REFERENCES:
patent: 4918677 (1990-04-01), Ashinuma et al.
patent: 5258877 (1993-11-01), Leake et al.
patent: 5327302 (1994-07-01), Khoury et al.
patent: 5341249 (1994-08-01), Abbott et al.

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