Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Patent
1997-07-10
1999-11-16
Chin, Stephen
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
H04L 700
Patent
active
059870826
ABSTRACT:
To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9.times.Si-9.times.Si+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.
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U.S. application No. 08/887,519, filed Jul. 3, 1997.
Chin Stephen
Ghayour Mohammad
Sony Corporation
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