Playback apparatus and playback method

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

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H04L 700

Patent

active

059870826

ABSTRACT:
To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) supplied thereto by the adder by four bits toward the LSB and outputs the right-shifted value (Si-1-9.times.Si-9.times.Si+1+Si+2)/16 to a second interpolation circuit as a first interpolation value Si' along with the sampled values Si and Si+1. As a result, the number of sampled values seemingly appears increased.

REFERENCES:
patent: 4672597 (1987-06-01), Yamazaki
patent: 4704711 (1987-11-01), Gerard et al.
patent: 5440532 (1995-08-01), Yokogawa et al.
patent: 5553055 (1996-09-01), Yokota et al.
patent: 5559513 (1996-09-01), Rothermel et al.
patent: 5579004 (1996-11-01), Linz
patent: 5589830 (1996-12-01), Linz et al.
patent: 5590100 (1996-12-01), Ogusu et al.
patent: 5848047 (1998-12-01), Fujimoto
U.S. application No. 08/887,519, filed Jul. 3, 1997.

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