Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Involving measuring – analyzing – or testing
Reexamination Certificate
2000-04-07
2003-01-28
Nguyen, Nam (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Involving measuring, analyzing, or testing
C205S123000, C205S149000, C205S150000, C205S157000, C205S261000, C205S296000, C205S297000, C205S298000
Reexamination Certificate
active
06511588
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a plating method, a plating solution, a semiconductor device and process for producing the device. In more particular, it relates to a plating method and a plating solution used in producing semiconductor devices having wiring and holes, to a process for producing a semiconductor device and to a semiconductor device produced by using them.
A known technology used for copper plating wiring and filling thereof into a semiconductor device in a process reported in “Demacene copper electroplating for chip interconnections”, P. C. Andricacos et al., IBM Research Development pp. 567-573, Vol. 42, No. 5, September 1998 (the first known technique) which comprises making copper grow selectively from the bottom of a hole or a trench by utilizing an additive thereby to fill the hole or the trench.
With regard to copper plating which utilizes an additive, there are known JP-A 2-104690 and JP-A 4-358091.
To attain a high speed operation of the integrated circuit of a semiconductor device, it has become of essential importance to develop a method for decreasing the wiring resistance, more specifically, to develop a process which utilizes copper wiring of low resistance in place of aluminum wiring previously used. With regard to the plating technique for copper wiring and hole filling, at present, the electroplating technique is the most promising candidate from the viewpoints of cost and filling characteristics. When the width of a hole or a trench to be filled by copper plating is small, seams or voids are apt to be generated in the copper film, resulting in an increase of resistance.
To avoid this difficulty, there has been disclosed a plating method in which an additive capable of deterring copper plating is added into the plating solution, whereby copper is grown preferentially from the bottom of the hole and the generation of seams and voids is prevented (a first known technique).
However, the generation of voids and seams in the hole and trench cannot be predicted simply from the characteristic properties of the additive. Therefore, there has been a disadvantage in that the filling performance of a plating solution has to be judged from the shape of the filled product obtained by actually filling a hole or trench by a plating method using a plating solution containing an additive material. Further, it has been necessary to develop and optimizing a plating solution every time the shape of the hole or trench changes.
Furthermore, the filling characteristics of a plating solution sometimes change with the lapse of time. To suppress the change, it is necessary to monitor the filling characteristics of the plating solution.
On the other hand, JP-A 2-104690 and JP-A 4-358091 aim at depositing copper plating uniformly with through holes as the object, so that they are different from the present invention in the object and the aim.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a plating method which uses a plating solution containing an additive having characteristic property conditions corresponding to the intended system, a plating solution containing the additive, a process for producing a semi-conductor device and a semiconductor device produced by the process. As a result, the generation of voids and seams can be deterred. Another object of the present invention is to specify the physical quantities to be determined with regard to filling characteristics thereby to deter the change of filling characteristics with time.
According to the present invention, there is provided a plating method which comprises, adding an additive which hinders growth of plating metal film to a plating solution so as to satisfy the following conditions:
0.005×
h
2
/w<D/&kgr;<
0.5×
h
2
/w
wherein D is a diffusion coefficient (m
2
/sec) of the additive; &kgr; is a surface reaction rate (m/sec) of adsorption or consumption of the additive; h is a height (m) of a trench or hole; and w is the minimum width (m) of the trench or the minimum radius (m) of the hole, and
0.01≦&THgr;≦0.7
wherein &THgr; is a ratio of (plating film growth rate in the presence of additive)/(plating film growth rate in the absence of additive), or (plating current in the presence of additive)/(plating current in the absence of additive) at the same plating potential, in the case of filling the trench having the width of 10
−6
m or less, or the hole having the radius of 10
−6
m or less, and forming the plating metal in the trench or hole.
According to the present invention, there are further provided a plating solution used in the above-mentioned plating method, a process for producing a semiconductor device using the plating method and the plating solution, and a semiconductor device thus obtained, said semiconductor device being able to have a multilayer structure of copper wiring layers formed on a semiconductor substrate by using the above-mentioned plating solution for forming each layer.
REFERENCES:
patent: 6024857 (2000-02-01), Reid
patent: 6113771 (2000-09-01), Landau et al.
patent: 6210555 (2001-04-01), Taylor et al.
patent: 2-104690 (1990-04-01), None
patent: 4-358091 (1992-12-01), None
Andricacos, et al., “Damascene Copper Electroplating For Chips Interconnections”, in IBM J. Res. Develop., vol. 42, No. 5, Sep. 1998, pp. 567-574.
Akahoshi Haruo
Fukada Shinichi
Haba Toshio
Itabashi Takeyuki
Kobayashi Kinya
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
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