Platform architecture and method for making same

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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C710S305000

Reexamination Certificate

active

08072971

ABSTRACT:
The present invention provides an architecture for a platform, which includes (1) gates located in a central area of a die for supporting an application layer; (2) a SerDes region located at one side of the die for holding at least one SerDes device; (3) a Link Layer Controller region, located adjacent the SerDes region and between the SerDes region and the gates, for supporting the at least one SerDes device; and (4) at least one RAM array for supporting the at least one SerDes device, the at least one RAM array being located at least one of adjacent the gates or between the gates and the Link Layer Controller region.

REFERENCES:
patent: 6901072 (2005-05-01), Wong
patent: 6928022 (2005-08-01), Cho et al.
patent: 2001/0009523 (2001-07-01), Maeno
patent: 2003/0217215 (2003-11-01), Taborek et al.
patent: 2004/0017815 (2004-01-01), Huff
patent: 2004/0022238 (2004-02-01), Kimmitt
patent: 2004/0068593 (2004-04-01), Helenic et al.
patent: 2004/0114622 (2004-06-01), Nation et al.
patent: 2004/0116120 (2004-06-01), Gallagher et al.
patent: 2005/0117388 (2005-06-01), Cho et al.
patent: 2005/0175018 (2005-08-01), Wong

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