Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-03-04
2001-10-23
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S711000, C257S774000, C257S773000, C257S784000, C257S780000, C257S700000, C257S698000
Reexamination Certificate
active
06307259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer plastic package within which a semiconductor chip is accommodated, and in particular to an innovative structure for a multi-layer plastic package within which a power source bonding pad and a power source plane layer are directly connected through the side wall of an opening in order to reduce the inductance of a power source.
2. Related Arts
A plastic pin grid array package (PPGA), or a plastic ball grid array package (PBGA) has become popular as a package for accommodating an LSI chip for which large number of input/output terminals are required. For example, a large LSI chip which requires the large number of input/output terminals, such as ASICs, can be accommodated within a package in which external terminals are arranged in the form of a grid. A multi-layer structure is employed for such a package because in addition to a signal wiring layer for the connection of signal input/output terminals, power source plane layers are provided for a supply of power and for a ground.
Instead of a conventional package, wherein are laminated a plurality of ceramic substrates, a plastic package has been proposed for use as a multi-layer LSI package. In the design of the plastic package, similar to a printed circuit board, core layers made of resin and formed conductive layers, and pre-impregnated layers, which are also made of resin, for bonding with the core layers are laminated.
With recently available devices, frequency and power consumption tend to be increased, and an appropriate structure for these factors is required for a package in which a chip can be accommodated. For example, first, a package is multi-layered, with a power source plane layer and a ground plane layer being provided in order to ensure the supply of a constant, large current. Second, the inductances in the power source plane layer and the ground wiring are reduced to the extent possible. Third, a power source and a ground plane layer are sandwiched between signal wiring layers to match the impedances of the signal lines. Fourth, crosstalk occurring between the signal lines is reduced. And finally, the change of the potentials in the power source and the ground are reduced to the extent possible.
In line with the above, a package has been proposed wherein a grounding bonding pad and a grounding plane layer are directly connected using a side wall conductance layer, which is formed on the side wall of an insulating layer.
However, with the conventionally proposed package structure, inductance can not be reduced for both a power supply source and a ground power source (in this specification, the power supply source and the ground power source are called power sources. Therefore, the power supply source is referred to as a first power source, and the ground power source is referred to as a second power source).
Furthermore, recent LSI devices have a plurality of types of power supply sources and a plurality of types of ground power sources. For such a device, the power supply source and the ground power source must be separately provided for a package prepared for the accommodation of an LSI chip. And it is difficult to reduce the inductance of all of the power sources.
In addition, since a side wall conductive layer is provided, a short circuit may occur with a bonding wire that is connected to a signal bonding pad. Further, a die attachment material on a die stage may short-circuit with a side wall conductive layer by forming a side wall conductive layer.
A package structure which can satisfactorily cope with the many conditions enumerated above has not yet been proposed.
SUMMARY OF THE INVENTION
It is, therefore, one objective of the present invention to provide a plastic package which can reduce the inductance of a power supply source and of a ground power source.
It is another objective of the present invention to provide a plastic package which can reduce the inductances of a plurality of types of power supply sources and of a ground power source.
It is an additional objective of the present invention to provide a plastic package which can prevent the occurrence of a short circuit due to a side wall conductive layer which reduces the inductance of a power source.
It is a further objective of the present invention to provide a plastic package which can adequately acquire impedance matching for signal wiring and which reduces crosstalk between signal lines.
To achieve the above objectives, according to the present invention, for a multi-layer plastic package having bonding pads at multiple levels, a plurality of electrically independent side wall conductive layers can be provided by forming side wall conductive layer on the side wall of an opening in each insulating layer. In particular, when the insulating layer forms a multi-layer structure, side wall conductive layers are formed on each of the individual side walls of the multi insulating layers, and a pre-impregnated layer is inserted between each two insulation layers, so that a plurality of electrically independent side wall conductive layers can be provided. Even for an insulating layer having a single layer structure, side wall conductive layers are formed so as to be electrically separated from each other, so that a plurality of side wall conductive layers can be provided. According to the present invention, the thus structured side wall conductive layers are properly combined, so that multiple side wall conductive layers can be provided for a multi-layer plastic package. Therefore, via the side wall conductive layers, many power source plane layers formed on the reverse surface of an insulating layer can be independently connected, at low inductances, to conductive layers, such as bonding pads, on the obverse surface of the insulating layer.
Furthermore, in a multi-layer plastic package according to the present invention the side wall of a conductive layer is covered by an insulating coating layer. Therefore, short circuits between the side wall conductive layer and the bonding wire can be prevented. Further, short circuits can be prevented between the die attachment material for bonding an LSI chip to a support substrate and the side wall conductive layer or the bonding wire.
To achieve the above objectives, according to the present invention, a plastic package for accommodating a semiconductor chip comprises:
a first insulating layer, in which a first opening is formed to accommodate the semiconductor chip, having a plurality of bounding pads including a first power source bonding pad formed on the obverse surface around the first opening, having a first power source plane layer formed on the reverse surface, and having a first side wall conductive layer, formed on the side wall of the first opening, for connecting the first power source bonding pad on the obverse surface to the first power source plane layer on the reverse surface;
a second insulating layer laminated to the first insulating layer, in which a second opening larger than the first opening is formed, having a plurality of bonding pads including a second power source bonding pad which is formed on the obverse surface and around the second opening, having a second power source plane layer formed on the reverse surface, and having a second side wall conductive layer, formed on the side wall of the second opening, for connecting the second power source bonding pad on the obverse surface to the second power source plane layer on the reverse surface;
a support substrate provided at the first opening for mounting the semiconductor chip thereon; and
first and second external power source terminals connected to the first and the second power source plane layers respectively.
Furthermore, to achieve the above objectives, according to the present invention, a plastic package for accommodating a semiconductor chip comprises:
a first insulating layer, in which an opening is formed for accommodating the semiconductor chip, having a plurality of bounding pads including a first power source bonding pad
Abe Mitsuo
Asada Kenji
Hamano Toshio
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Thoi Luan
Thomas Tom
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