Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
1998-06-04
2001-05-15
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S003000, C438S112000
Reexamination Certificate
active
06232153
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to a plastic package assembly method, and more particularly to a “ferroelectric friendly” plastic package assembly method suitable for improving the retention performance and reliability of ferroelectric memory circuits.
Ferroelectric memory products generally exhibit poor performance in plastic packages as compared to other packaging options such as ceramic packages. One of the chief causes of the poor performance is the elevated temperatures that the ferroelectric integrated circuit is exposed to for extended times during plastic package assembly. Typically, combined cures performed during plastic package assembly of ferroelectric memories can be as long as ten hours at temperatures that can activate undesirable imprint mechanisms as these temperatures approach the Curie point of the ferroelectric dielectric material used. Current assembly methods use ink cures, wafer mount cures, die attach cures, wire bonding, die coat cures, molding, molding cures, as well as back and top marking cures. Each of these processing steps contribute to the time spent at an elevated temperature, which can adversely affect electrical performance.
A typical prior art plastic package assembly flow
10
is shown in FIG.
1
. Note that not every plastic package assembly step is shown in
FIG. 1
, only those steps having a significant “time at temperature” exposure, and that are significantly altered in the plastic packaging method of the present invention, which is described in further detail below.
A typical die attach step
12
is referenced in
FIG. 1
, which is usually performed at a temperature of 175° C. or more for at least an hour. A typical die coat and curing step
14
is referenced in
FIG. 1
, which is usually performed at a temperature of 150° C. or more for at least two hours. After the plastic package is formed during a molding step, a typical post mold curing step
16
is referenced in
FIG. 1
, which can be performed at a temperature of 175° C. or more for at least five hours. After the package is inked, a typical back mark curing step
18
is referenced in
FIG. 1
, which can be performed at a temperature of 175° C. or more for at least two hours. A typical front or top mark curing step
20
is referenced in
FIG. 1
, which can be performed at a temperature of 175° C. or more for at least two hours.
The adverse effects of time spent at temperature for ferroelectric devices can be further analyzed with respect to a hysteresis loop, which is a representation of the charge versus voltage characteristics of a ferroelectric device. A typical hysteresis loop
22
for a ferroelectric capacitor is shown in FIG.
2
. The size and shape of hysteresis loop
22
can be used to characterize the electrical performance of a ferroelectric capacitor, and can also be used to diagnose the degradation of electrical performance due to exposure at elevated temperatures for extended times. Data retention reliability can be adversely affected by changes in the ferroelectric capacitor due to exposure of the integrated circuit at elevated temperatures for extended times. Switched charge (Q
sw
) loss due to thermal depolarization at elevated temperatures approaching, but not exceeding, the Curie point affect the retention performance of the completely fabricated, plastic packaged ferroelectric memory. Asymmetry, which is the undesirable shift in hysteresis loop
22
along the voltage (X) axis, is also impacted as a result of extended times at elevated temperatures. With reference to the P, U, N, and D charge components associated with hysteresis loop
22
of
FIG. 2
, switched charge and asymmetry are defined as follows:
Q
sw
=((
N−D
)+(
P−U
))/2 [1]
Asymmetry=((
P−U
)−(
N−D
))/2 [2]
Asymmetry and loss of switched charge are linked and are both adversely affected by conventional plastic package assembly methods that are otherwise suitable for non-ferroelectric based integrated circuits.
What is desired, therefore, is a plastic package assembly method that greatly reduces the undesirable impact on electrical performance of a ferroelectric integrated circuit due to loss in switched charge and increased asymmetry due to exposure to elevated temperatures for extended periods of time.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to maximize the yield and reliability of ferroelectric integrated circuit memories and other ferroelectric-based integrated circuits during and subsequent to plastic packaging.
According to the present invention, a “ferroelectric friendly” plastic package assembly method includes a strict thermal budget that reduces the time at temperature for four key processing steps: die attach cures, die coat cures, molding cures, and marking cures, while still providing a suitable plastic package for a ferroelectric-based integrated circuit. The plastic package assembly method of the present invention uses low temperature mold and die coat materials, as well as low temperature curable inks or laser marking in order to minimize degradation of electrical performance, thus improving manufacturing yields and reliability.
In part, the method of the present invention uses a snap cure die attach step, a die coat followed by a room temperature cure, and forming the plastic package with room temperature curable molding compounds not requiring a post mold cure. Top and back marking of the plastic package is accomplished using an infrared ink followed by minimum cure time at elevated temperature, by using laser marking, or by using ultraviolet curable ink.
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Lau Vic
Mitra Sanjay
Burton Esq. Carol W.
Elms Richard
Meza, Esq. Peter J.
Pyonin Adam
Ramtron International Corporation
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