Plastic molded type semiconductor device and fabrication...

Details Plastic molded type semiconductor device and fabrication... Plastic molded type semiconductor device and fabrication...

2001-04-11

2003-05-06

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S118000, C438S123000, C438S124000, C438S127000

Reexamination Certificate

active

06558980

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a plastic molded type semiconductor device; and, in particular, the invention relates to a plastic molded type semiconductor device fabricated by the transfer mold method and to a technique effective when applied to a process for the fabrication of the device.
A plastic molded type semiconductor device is fabricated by mounting a semiconductor chip on a chip mounting surface of a die pad (which is also called a tab) supported on the frame body of a lead frame through a supporting lead; electrically connecting an external terminal, which is disposed on the principal surface of the semiconductor chip, with an inner portion of the lead supported on the frame body of the lead frame through a bonding wire; sealing the semiconductor chip, die pad, supporting lead, inner portion of the lead, bonding wire and the like with a plastic mold; cutting the supporting lead and the outer portion of the lead from the frame body of the lead frame; and then forming the outer portion of the lead into a predetermined shape.
The plastic mold for the above-described plastic molded type semiconductor device is fabricated in accordance with a transfer mold method suited for mass production. Described specifically, a lead frame subjected to the preceding steps (die bonding step and wire bonding step) is disposed between the top portion and the bottom portion of a mold and, at the same time, within the cavity of the mold, a semiconductor chip, die pad, supporting leads and inner portions of the leads and bonding wires are arranged. Then, a resin is poured under pressure into the cavity from a pot of the mold through its runner and gate, whereby a plastic mold can be prepared.
In the fabrication step of the above-described plastic mold, with a view toward avoiding a failure to completely fill the cavity, in other words, for suppressing the generation of a void, there has been an attempt to make the fluidity of the resin flowing into the filling region
11
A on the principal surface side of the semiconductor chip
2
equal to the fluidity of the resin flowing into the filling region
11
B on the reverse surface side of the semiconductor chip
2
by arranging the semiconductor chip
2
and the die pad
3
A within the cavity
11
, as illustrated in
FIG. 16
(a schematic cross-sectional view), so as to make a clearance L
1
from the principal surface of the semiconductor chip
2
to the inside wall surface of the cavity
11
opposite to the principal surface equal to a clearance L
2
from the reverse surface of the die pad
3
A to the inside wall surface of the cavity
11
opposite to the reverse surface. In addition, there has also been an attempt to cause the resin to flow simultaneously into the filling region
11
A on the principal surface side of the semiconductor chip
2
and the filling region
11
B on the reverse surface side by adopting, as a gate for controlling the amount of the resin poured into the cavity
2
, a center gate
12
(which will also be called a “vertical gate”) extending above and below the lead frame
3
.
In the above-described plastic molded semiconductor device, the die pad, together with the semiconductor chip, is sealed with the plastic mold so that water contained in the plastic mold tends to be collected on the reverse surface of the die pad. Water collected on the reverse surface of the die pad vaporizes and expands in response to the heat generated during a temperature cycle test, which is an environmental test effected after the completion of the product, or the heat generated upon packaging, and becomes a cause for the generation of cracks (package cracks) in the plastic mold.
With a view toward overcoming such technical problems, Japanese Patent Laid-Open No. SHO 63-204753 discloses a technique for making the area of a die pad smaller than that of a semiconductor chip, by which technique, the phenomenon causing water contained in the resin of a plastic mold to be collected on the reverse surface of the die pad can be suppressed. Thus, cracks (package cracks) in the plastic mold caused by vaporization and expansion of the water contained on the reverse surface of the die pad can be prevented.
As illustrated in
FIG. 17
(a schematic cross-sectional view), when the area of a die pad
3
A is made smaller than that of a semiconductor chip
2
, a filling region
11
B on the reverse surface side of the semiconductor chip
2
becomes wider in proportion, which makes the fluidity of a resin flowing in the filling region
11
B on the reverse surface side of the semiconductor chip
2
to be higher than that flowing in the filling region
11
A on the principal surface side of the semiconductor chip
2
. In other words, the filling of the resin into the filling region
11
B on the reverse surface side of the semiconductor chip
2
is completed earlier than that flowing into the filling region
11
A on the principal surface side of the semiconductor chip
2
. As illustrated in
FIG. 18
(a schematic cross-sectional view), a resin
1
A flowing in the filling region
11
B on the reverse surface side of the semiconductor chip
2
lifts the semiconductor chip
2
upwardly and causes an inconvenient shifting of the semiconductor chip
2
, bonding wire and the like from the plastic mold, leading to a marked reduction in the yield of the plastic molded type semiconductor device.
In the resin molded type semiconductor device adopting a QFP structure, on the other hand, supporting leads are arranged in the outside region at the corner of a semiconductor chip, while a plurality of leads and a plurality of bonding wires are arranged in the outside region on each side of the semiconductor chip. In other words, the outside region at the corner of the semiconductor chip is coarser than the outside region on each side of the semiconductor chip so that the fluidity of the resin is higher in the outside region at the corner of the semiconductor chip than it is in the outside region on each side of the semiconductor chip. Accordingly, the bonding wire tends to move owing to the resin flowing into the outside region on each side of the semiconductor chip from the outside region at the corner, and a short circuit occurs between two adjacent bonding wires, which brings about a marked deterioration in the yield of the plastic molded type semiconductor device. The short circuit between these bonding wires is particularly marked between a bonding wire connected to a first-stage lead most closely adjacent to the outside region at the corner of the semiconductor chip and a bonding wire connected to a second-stage lead adjacent to the first lead.
An object of the present invention is to provide a technique which can increase the yield of a plastic molded type semiconductor device.
Another object of the present invention is to provide a technique which can heighten the yield in the fabrication process of a plastic molded type semiconductor device.
The above-described and the other objects and novel features of the present invention will be apparent from the following description and accompanying drawings.
SUMMARY OF THE INVENTION
Typical aspects of the invention as disclosed in this application will next be summarized briefly.
(1) A process for the fabrication of a plastic mold semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold, which comprises a step of mounting the semiconductor chip on the principal surface of the die pad supported onto a frame body of a lead frame through supporting leads; a step of arranging said lead frame between the top portion and the bottom portion of a mold and arranging, in a cavity of the mold, the semiconductor chip and die pad so that a clearance from the reverse surface side of the die pad to the inside wall surface of the cavity opposite to the reverse surface side of the die pad becomes narrower, by the thickness of the die pad, than a clearance from the

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