Plastic molded pin grid chip carrier package

Details Plastic molded pin grid chip carrier package Plastic molded pin grid chip carrier package

1987-11-13

1989-09-19

Hille, Rolf

357 74, H01L 2348, H01L 2312

Patent

active

048686387

ABSTRACT:
An improved plastic molded chip carrier package for a semiconductor chip has a plurality of I/O pins arranged on a pin grid array. The pin grid array comprises at least two rows of the I/O pins disposed along the sides of the chip in such a manner that the I/O pins are staggered with respect to those in the other row. The staggered arrangement of the I/O pins makes it easy to provide electrical interconnection between the I/O ports on the chip and the corresponding I/O pins without requiring an elaborate or crowded wiring or connection lines. This is particularly effective when an increased number of the I/O pins are required to be included in the limited area of the chip carrier.

REFERENCES:
patent: 4326214 (1982-04-01), Trueblood
patent: 4338621 (1982-07-01), Braun
patent: 4530002 (1985-07-01), Kanai
patent: 4618739 (1986-10-01), Theobald
patent: 4700473 (1987-10-01), Freyman et al.
patent: 4723156 (1988-02-01), Okuaki
"Eighty-Pin Package for Field-Effect Transistor Chips"-Honn-IBM Technical Disclosure Bulletin-vol. 15-No. 1, 6-1972, p. 308.
"Flanged Pin MC Substrate Design"-Funari et al., IBM Tech. Disclosure-vol. 21, No. 1-6-1978, pp. 94-95.
IBM Technical Disclosure-vol. 15, No. 3-Aug. 1972-Connector Interposer for Module to Board Elec. Interconnection-Agard et al.--p. 912.
Solid State Technology, vol. 25, No. 6, Jun. 1982, pp. 94-100.
Electronics, Mar. 17, 1987, pp. 81-91.
IBM Technical Disclosure Bulletin, vol. 21, No. 8, Jan. 1979, p. 3120.

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