Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1996-05-20
1997-12-23
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438732, 438905, 216 67, 134 12, H01L 2100
Patent
active
057007411
ABSTRACT:
A method for limiting contaminant particle deposition upon integrated circuit layers within plasma assisted process reactor chambers. First, there is undertaken a plasma assisted process upon an integrated circuit layer within a plasma assisted process reactor chamber. The plasma assisted process employs a reactant gas composition, a first radio frequency power and a first reactor chamber pressure appropriate to the plasma assisted process and the integrated circuit layer. There is then undertaken a first plasma purge step for a first purge time immediately following the plasma assisted process. The first plasma purge step employs a first purge gas composition, a second radio frequency power and a second reactor chamber pressure. The second radio frequency power is lower than the first radio frequency power and the second reactor chamber pressure is higher than the first reactor chamber pressure. Optionally, there may also be undertaken a second plasma purge step for a second purge time immediately following the first plasma purge step. The second plasma purge step employs a second purge gas composition, a third radio frequency power and a third reactor chamber pressure. The third radio frequency power is no greater than the second radio frequency power and the third reactor chamber pressure is lower than the second reactor chamber pressure.
REFERENCES:
patent: 5403780 (1995-04-01), Jain et al.
patent: 5637190 (1997-06-01), Liao
patent: 5647953 (1997-07-01), Williams et al.
Ackerman Stephen B.
Powell William
Saile George O.
Szecsy Alek P.
Vanguard International Semiconductor Corporation
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