Plasma etching method

Details Plasma etching method Plasma etching method

2000-11-08

2003-07-08

Beck, Shrive P. (Department: 1763)

Etching a substrate: processes

Forming groove or hole in a substrate which is subsequently...

C216S067000, C216S079000, C438S733000, C438S738000, C438S743000

Reexamination Certificate

active

06589435

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming holes, by means of plasma etching, in an insulating film, which consists essentially of silicon oxide and is disposed on a substrate, such as a semiconductor wafer. The holes are formed from the top surface of the insulating film down to wiring layers, which are embedded in the insulating film and located at different depths from the top surface.
2. Discussion of the Background
For processes of manufacturing semiconductor devices, wiring structures have become multi-wiring layer structures, in response to a recent demand that the devises should have high density and high integrity. Accordingly, techniques for electrical inter-connection among layers have become important, in relation to a contact hole for connecting a lower semiconductor to an upper wiring layer, and a via-hole for connecting upper and lower wiring layers to each other.
In these kind of techniques, wiring layers are becoming minute, and thus are increasingly required to be thinner. For this reason, some conditions need to be considered when via-holes or contact holes are formed, relative to wiring layers, by etching. For example, as shown in
FIG. 6
, there are cases where the diameter of an opening
103
for a contact hole is larger than the width of a wiring layer
102
, and where an opening
105
for a hole is located at a position slightly shifted from a wiring layer
104
due to mask shifting. Furthermore, as shown in
FIG. 7
, there is a case where wiring layers are disposed on different levels on the basis of the influence of the underlying layer. In
FIGS. 6 and 7
, reference symbols
101
and
106
denote a silicon oxide insulating film and a resist pattern, respectively.
As shown in
FIG. 7
, where wiring layers are present at different depths in an inter-level insulating film, and a contact hole is slightly shifted from the wiring layer at the shallower position, over-etching is caused on the wiring layer
108
at the shallower position when etching is performed down to the wiring layer
107
at the deeper position. In this case, that part of the insulating film adjacent to the wiring layer
108
at the shallower position is etched, and there may be formed a short-circuit between the wiring layer
108
and a wiring layer
109
thereunder
SUMMARY OF THE INVENTION
An object of the present invention is, in a plasma-etching method of forming holes relative to wiring layers present at different depths in an insulating film, to reliably etch the insulating film down to the wiring layer at the deeper position, and to prevent that part of the insulating film adjacent to the wiring layer at the shallower position from being over-etched.
In light of this object, the present inventors conducted experiments on processes of anisotropically etching an insulating film of silicon oxide, while using plasma of a process gas including a fluorocarbon-containing gas, such as C
4
F
8
gas or C
5
F
8
gas, to form holes in the insulating film. As a result, the present inventors have found that, where the ratio of a fluorocarbon-containing gas, such as C
4
F
8
gas or C
5
F
8
gas, relative to the whole process gas is extremely low as compared to conventional values, it is possible to reliably etch the insulating film down to a wiring layer at a deeper position, and to prevent that part of the insulating film adjacent to a wiring layer at a shallower position from being over-etched.
According to a first aspect of the present invention, there is provided a method of forming first and second holes, by means of plasma etching, in an insulating film, which consists essentially of silicon oxide and is disposed on a substrate, such that the first and second holes are formed from a top surface of the insulating film down to first and second wiring layers, which are embedded in the insulating film and located at different depths from the top surface, the method comprising the steps of:
placing the substrate in an airtight process chamber;
supplying a process gas comprising a fluorocarbon-containing gas into the process chamber, while exhausting the process chamber; and
turning the process gas into plasma, and anisotropically etching the insulating film with the plasma,
wherein, in the process of anisotropically etching the insulating film, the process chamber is set to have an inside pressure of from 30 to 60 mTorr, and the fluorocarbon-containing gas is set to have a partial pressure of from 0.07 to 0.35 mTorr in the process chamber.
In the present invention, the ratio of the fluorocarbon-containing gas in the process gas is set low, whereby etching deposits onto the wiring layer at the shallower position increase, so that the etching is prevented from proceeding beyond the wiring layer at the shallower position. Where the partial pressure of the fluorocarbon-containing gas is set to fall in the above described range, etching the insulating film down to the wiring layer at the deeper position is ensured. Typically, the fluorocarbon-containing gas consists of C
4
F
8
gas or C
5
F
8
gas.
Where the process gas contains CO, the CO reacts with F, which is one of the etching residues, to form a compound, and then the compound is exhausted out of the system. As a result, the etching selectivity increases, while deposited C is dissolved to accelerate the etching. Where the fluorocarbon-containing gas consists of C
4
F
8
gas or C
5
F
8
gas, the flow ratio of the CO gas relative to the C
4
F
8
gas or C
5
F
8
gas is preferably set to be from 35 to 200. With this condition, it is ensured to etch the oxide film down to the wiring layer at the deeper position, while preventing the insulating film from being over-etched around the wiring layer at the shallower position.
Where the process gas contains a hydrogen-containing gas, it is possible to accelerate the etching reaction to increase the etching rate. For example, where CHF
3
gas or CH
2
F
2
gas is used as the hydrogen-containing gas, and the composition ratios of the process gas are appropriately adjusted, the etching rate is increased by 20% or more, as compared to a case where the hydrogen-containing gas is not contained.
Where the fluorocarbon-containing gas consists of C
4
F
8
gas or C
5
F
8
gas, and the hydrogen-containing gas consists of CHF
3
gas or CH
2
F
2
gas, the flow ratio of the hydrogen-containing gas relative to the fluorocarbon-containing gas is preferably set to be from 1 to 5. Where the flow ratio is more than five, the etching is disturbed by an excessive amount of the hydrogen-containing gas, and may not reach the wiring layer at the deeper position. On the other hand, where the flow ratio is less than one, the effect of the added hydrogen-containing gas is not sufficiently exhibited.
The process gas preferably further contains an inactive gas.
The present invention is particularly effective in a case where the second wiring layer is located at a position shallower than that of the first wiring layer, and the opening of the second hole on the surface of the insulating film is set to overlap with the orthogonal projection of the second wiring layer on the surface of the insulating film by a degree of not less than one-fourth but less than one times the area of the opening. Where this area ratio is one-fourth or more, the etching is easily stopped at the wiring layer at the shallower position. Where the orthogonal projection of the second wiring layer and the opening of the second hole completely overlap with each other, the insulating film around the wiring layer at the shallower position is never etched downward beyond it. Accordingly, only the case where the area ratio is less than one needs to be carefully considered.
Where the second wiring layer is present at a position shallower than the first wiring layer, the second wiring layer may be designed to have upper and lower layers stacked one on top of the other, in which the upper layer has a higher resistance against the process gas than that of the lower layer. With this arrangement, the second wir

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