Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-03-14
2003-03-04
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S066000, C345S067000, C345S068000, C345S204000, C345S211000, C313S581000, C313S582000, C313S584000, C315S169100, C315S169200, C315S169400
Reexamination Certificate
active
06529177
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving an AC discharge memory-operating type plasma display panel and to a plasma display device in which a plurality of scan electrodes and a plurality of data electrodes are arranged to intersect with each other, discharge is generated at the intersections of the scan electrodes and the data electrodes upon application of a desired data pulse to the data electrodes to effect and screen display.
2. Description of the Related Art
PDP (plasma display panels) generally offer many features, including thin construction, a low level of flicker, a high display contrast ratio, relative ease of application to large screens, and a high response speed. In addition, PDP are self-light emitting and are therefore capable of multicolor emission through the use of phosphors. Due to these features, the use of PDP has been expanding in recent years in the fields of large public display devices and color television.
PDP include the ac-discharge type, in which electrodes are covered by a dielectric, that operates in a state of indirect AC discharge; and the dc discharge type, in which electrodes are exposed in a discharge space, that operates in a direct-current discharge state.
The ac discharge type includes a memory-operating type that uses the memory of a discharge cell; and a refresh-operation type that does not use the memory of a discharge cell. The luminance of both the memory-operating type of PDP and the refresh operation type of PDP is substantially proportional to the number of discharges, i.e., the number of repeated voltage pulses. The refresh operation type of PDP exhibits a decrease in luminance if the display capacitance is increased, and this type of PDP is therefore used in PDP having little display capacitance.
FIG. 1
is a perspective sectional view showing the construction of a display cell in an ac-discharge memory-operating type of PDP. The PDP comprised by: insulating substrates
1
and
2
, scan electrodes
3
, sustain electrodes
4
, bus electrodes
5
and
6
, data electrodes
7
, discharge gas space
8
, phosphor
11
, dielectric layer
12
, protective layer
13
, dielectric layer
14
, and barriers
9
.
The front surface and back surface, i.e., insulating substrates
1
and
2
, are made of glass. Transparent scan electrodes
3
and transparent sustain electrodes
4
are formed on insulating substrate
2
. Bus electrodes
5
and
6
are arranged to overlie scan electrodes
3
and sustain electrodes
4
to reduce the electrode resistance. Data electrodes
7
are formed on insulating substrate
1
orthogonal to scan electrodes
3
and sustain electrodes
4
. Discharge gas space
8
is the space between insulating substrate
1
and insulating substrate
2
and is filled with a discharge gas that is composed of helium, neon, or xenon, or a compound gas of these gases. Phosphor
11
converts the ultraviolet light that is generated by discharge of the discharge gas to visible light
10
. Dielectric layer
12
covers scan electrodes
3
and sustain electrodes
4
. Protective layer
13
is a layer made of magnesium oxide or the like and protects dielectric layer
12
from discharge. Dielectric layer
14
covers data electrodes
7
. Barriers
9
partition display cells from other adjacent display cells. The surface of data electrodes
7
is covered by dielectric layer
14
. A plurality of barriers
9
are provided on the surface of dielectric layer
14
. Phosphor
11
is applied to the surface of dielectric layer
14
between adjacent barriers
9
and to the side surfaces of barriers
9
.
FIG. 2
is a vertical section of a single display cell in the AC discharge memory-operating type of PDP shown in FIG.
1
.
The discharge operation of the selected display cell is next described with reference to FIG.
2
. Discharge occurs when a pulse voltage that exceeds a discharge threshold value is applied between scan electrode
3
and data electrode
7
. When discharge occurs, the positive and negative charges that are generated by the discharge are absorbed into the surfaces on both sides, i.e., into the surface of dielectric layer
12
and phosphor
11
, and charge accumulation takes place according to the polarity of the applied pulse voltage. This charge is hereinbelow referred to as “barrier charge.” The equivalent internal voltage that is generated by the accumulation of this charge at the two ends of discharge gas space
8
(in
FIG. 2
, above and below the plane of the figure), i.e., barrier voltage, is of the opposite polarity of the pulse voltage. The effective voltage inside the display cell therefore drops with increase in the barrier charge even though the applied pulse voltage is kept at a fixed value. When the effective voltage inside the display cell falls to the extent that discharge can no longer be sustained, discharge ceases. If the polarity of the voltage that is applied to data electrode
7
is reversed at this time, the barrier charge is erased. Since the collision of positive charge of high mass with phosphor
11
shortens the life of the phosphor, a voltage that is positive with respect to scan electrode
4
is applied to data electrode
7
such that negative charge (electrons) of low mass are stored in the surface of phosphor
11
. In order to sustain discharge in this state, sustain electrodes
4
are provided parallel to scan electrodes
3
, and a sustaining discharge is continued between scan electrodes
3
and sustain electrodes
4
. Thus, after discharge between data electrode
7
and scan electrode
4
is initiated in a selected display cell that is to emit light, a sustaining discharge pulse, which is a pulse voltage of the same polarity as the barrier voltage, is applied between adjacent scan electrode
3
and sustain electrode
4
, whereby the effective voltage is equivalent to the barrier voltage added to the voltage of the sustaining discharge pulse. The effective voltage therefore exceeds the discharge threshold value even though the voltage of the sustaining discharge pulse is low, and discharge is thus sustained. Discharge is thus sustained through the application of sustaining discharge pulses alternately to scan electrode
3
and sustain electrode
4
. This function is the above-described memory function.
The sustain discharge is halted by applying, as an erase pulse, a wide pulse of low voltage or a narrow pulse of approximately the same voltage level as the sustaining discharge pulse to scan electrode
3
or sustain electrode
4
so as to neutralize the barrier voltage.
FIG. 3
is a block diagram showing: a PDP that is formed by arranging display cells such as shown in
FIG. 2
in a matrix, a control circuit, a scan driver, a sustain driver, and a data driver.
PDP
15
is a panel for dot matrix display in which mxn display cells
16
are arranged. In PDP
15
, scan electrodes X
1
, X
2
, . . . , Xm and sustain electrodes Y
1
, Y
2
, . . . , Ym arranged parallel to each other are provided as row electrodes; and data electrodes D
1
, D
2
, . . . , Dn arranged orthogonal to the row electrodes are provided as column electrodes.
Scan driver
21
applies a voltage of the scan electrode drive waveform to scan electrodes X
1
, X
2
, . . . , Xm. Sustain driver
22
applies a voltage of the sustain electrode drive waveform to sustain electrodes Y
1
, Y
2
, . . . , Ym. Data driver
50
applies a voltage of the data electrode drive waveform to data electrodes D
1
, D
2
, . . . , Dn.
Control circuit
60
generates signals for controlling data driver
50
, scan driver
21
, and sustain driver
22
based on vertical synchronizing signals Vsync, horizontal synchronizing signals Hsync, clock signals “Clock,” and display data signals DATA.
Display data signal DATA are signals indicative of the data that are to be displayed in each display cell. Vertical synchronizing signal Vsync is a signal indicative of the period of a frame in which a series of operations is concluded, from a preparatory discharge interval until an erase discharge interval, and the starting
Hjerpe Richard
NEC Corporation
Tran Henry N.
Whitham, Curtis and Christofferson, P.C.
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