Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-03-30
2004-04-20
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S063000, C345S068000, C345S211000
Reexamination Certificate
active
06724356
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a display unit (hereinafter, referred to as a plasma display unit (PDP unit)) using a plasma display panel (hereinafter, referred to as a PDP), and more particularly to a plasma display unit for displaying gradation by making the display luminescence time different by weighting every sub-frame.
In recent years, in display units, there have been growing demands for thinner units, increases of varieties of information to be displayed and installation conditions, larger screens and better resolution, and display units are required which can meet these demands. PDP units are display units which can handle these demands. In the PDP units, when displaying gradation, in general, a display frame is constituted by a plurality of sub-frames, the respective sub-frame periods are weighted so that they are differentiated, and the respective bits of gradation data are displayed by the corresponding subframes.
The PDP has a memory effect, and each cell is set for a state conforming to the display data. Luminescence for display (display luminescence) is effected by application of an AC voltage. As will be described later, this display luminescence intensity is varied by the number of the cells which are illuminated, and there is a problem in that the luminance ratio between the subframes deviates. In addition, consumed current and power also vary in accordance with the number of the cells which are illuminated. The present invention solves the problem entailed by the variation in display.
Regarding PDP types, there are two-electrode type PDPs in which selected discharge (address discharge) and maintained discharge (discharge for display luminescence) are carried out with two electrodes and a three-electrode type PDP in which a third electrode is used to carry out address discharge. Three-electrode type PDP units are disclosed in Japanese Unexamined Patent Publication (Kokai) Nos. 7-140928 and 9-185343, and therefore, a detailed description thereof will be omitted here and only the basic construction and operation thereof will be briefly described below.
FIG. 1
shows the basic construction of the three-electrode type PDP units. As shown therein, connected to a plasma display panel (PDP)
1
are an address driver
2
for outputting a signal to be applied to an address electrode, a Y scan driver
3
for outputting a signal to be applied to a scan electrode (Y electrode), an X common driver
4
for outputting a signal to be applied to a common sustaining discharge electrode (X electrode), and a Y common driver
5
for outputting a sustaining discharge signal to be applied to the Y electrode via the Y scan driver
3
. A control circuit
6
has a display data control part
7
for generating from a display data inputted from the outside a display data signal to be outputted to the address driver
2
and a panel driving control part
8
for outputting a signal other than the display data which is related to the driving of the panel. The panel driving control part
8
has a scan driver control part
9
for generating a control signal which is related to a scan to be outputted to the Y scan driver
3
and a common driver control part
10
for generating a control signal related to the sustaining discharge.
FIG. 2
shows a frame construction for carrying out a 32-gradation display.
A gradation display in the PDP unit is generally carried out by making each bit of the display data correspond to the sub-frame time and changing the length of the sub-frame period in accordance with the weighting of the bits. For instance, when the 32-gradation display is carried out, the display data is represented by five bits, the display of one frame is constituted by five sub-frames SF
1
to SF
5
, and the display of the respective bit data is carried out within the respective sub-frame periods. In reality, in order to control timings, there are provided rest periods when no operation is performed.
Each of the sub-frames SF
1
to SF
5
comprises a reset period during which all display cells of the panel are put in a uniform state, an addressing period during which wall electric charges corresponding to display data are accumulated in display cells, and a sustaining period during which a discharge for display is carried out by the display cells in which wall electric charges are accumulated by applying a sustaining discharge signal. As shown in
FIG. 2
, the respective lengths of the reset period and the addressing period are the same over the successive sub-frames, but the sustaining period is different. The respective lengths of the reset period and the address period of the successive sub-frames are identical. As described above, when the 32-gradation display is carried out, in general, the ratios between the respective lengths of the sustaining discharge periods becomes 1:2:4:8:16. The differences in luminance of 32 gradations from 0 to 31 can be displayed by selecting a combination of sub-frames to be illuminated in each display cell.
FIG. 3
is a block diagram showing a schematic construction of a part of a control circuit
6
′ related to the control circuit
6
′ of the present invention. Of the external input signals, the display data is inputted into a data converter
11
and a vertical synchronization signal (VSYNC) is inputted into a frame counter
12
. The display data that is supplied from the outside (i.e., the external display data) generally takes a format in which gradation data of respective pixels are continuous, and they cannot be converted into the format of the sub-frames as they are. To cope with this, the data converter
11
temporarily stores the display data in the frame memory and then converts it into a format for the address data to be outputted to the address driver
2
. Furthermore, the data converter calculates a load factor, which will be described later.
The frame counter
12
detects the length of one frame (frame length) from the vertical synchronization signal. There are various types of signals that are inputted from the outside, and it is generally true that PDP units are designed to deal with those signals by changing the control timing based on the frame length detected by the frame counter
12
. The number of sub-frames (SF number) and the luminance ratio of each thereof are stored in a driving table
17
for a memory (ROM)
16
in accordance with the frame length. An arithmetic unit
13
calculates an address CASE of the memory
16
in which corresponding information is stored, based on the frame length, applies the CASE so calculated on the memory
16
via a scan controller
15
and determines an SF number and a luminance ratio corresponding to the frame length.
The arithmetic unit
13
decreases a time required for the reset period and the addressing period from the SF number, calculates a sustaining discharge period in one frame and calculates a total sustaining pulse number for one frame from the sustaining discharge period and one predetermined sustaining pulse cycle. Sustaining pulse numbers of the respective sub-frames are stored in a luminance table
19
of a memory (ROM)
18
in accordance with the total sustaining pulse number and the luminance ratio. The arithmetic unit
13
calculates from the total sustaining pulse number an address MCB of the memory
18
in which corresponding information is stored, applies the address MCB so calculated together with the luminance ratio on the memory
18
and determines sustaining pulse numbers for the respective sub-frames. Conventionally, the respective sustaining numbers of the successive sub-frames are determined for control.
FIG. 4
shows an example of the luminance table
19
.
Next, the load factor and the consumed power will be described. The effective brightness of the display by the sub-frames of each frame is determined by the respective luminance and period of the sustaining discharge in each of the subframes. The sustaining discharge periods of the respective sub-frames have a predetermined ratio (luminance ratio) and, if the number (display load
Ishida Katsuhiro
Kojima Ayahito
Kuriyama Hirohito
Wakayama Hiroyuki
Yamamoto Akira
Chow Dennis-Doon
Fujitsu Limited
Staas & Halsey , LLP
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