Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1996-07-31
2002-04-16
Jankus, Almis R. (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S066000, C315S169400
Reexamination Certificate
active
06373452
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a surface discharge AC plasma display panel, a method of driving same and a plasma display apparatus employing same.
2. Description of the Related Art
The plasma display panel (PDP) has good visibility because it generates its own light, is thin and can be made with large-screen and high-speed display. For these reasons it is attracting interest as a replacement for the CRT display. A surface discharge AC PDP is especially suitable for full color display. Therefore, there are high expectations in the field of high-vision and the demand for a higher quality image is increasing. A higher quality image is achieved by generating higher definition, a higher number of gradations, better brightness, lower brightness for black areas, higher contrast and the like. High definition is achieved by narrowing the pixel pitch, a higher number of gradations is achieved by increasing the number of subfields within a frame, higher brightness is achieved by increasing the number of times a sustaining discharge is performed, and lower brightness for deeper blacks is achieved by reducing the quantity of light emission during the reset period.
FIG. 30
shows the schematic structure of an surface discharge AC plasma display panel (PDP)
10
P in the prior art.
On the observer-side of one of the glass substrates that face each other, electrodes X
1
to X
5
are formed in parallel to one another at an equal pitch, and electrodes Y
1
to Y
5
are formed in parallel to one another to form parallel pairs with the corresponding electrodes X
1
to X
5
. On the other glass substrate, address electrodes A
1
to A
6
are formed in the direction that runs at a right angle to the aforementioned electrodes, and phosphor covers on that. Between the glass substrates that face each other, partitioning walls
171
to
177
and partitioning walls
191
to
196
are arranged intersecting each other in a lattice, to ensure that no erroneous display is made through discharge of one pixel affecting adjacent pixels.
The surface discharge PDPs have an advantage in that the phosphor does not become degraded due to the impact of ions on it since discharge occurs between adjacent electrodes on the same surface. However, since a pair of electrodes is provided for each of the display lines L
1
to L
5
, the degree to which the pixel pitch can be reduced is limited and this is a stumbling block for achieving high definition. In addition, the scale of the drive circuit must be large since there is a high number of electrodes.
To deal with this problem, a PDP
10
Q as shown in
FIG. 31
has been disclosed in Japanese Patent Publication No. 5-2993 and No. 2-220330.
In the PDP
10
Q, partitioning walls
191
to
199
are provided on the central lines of the electrodes X
1
to X
5
and Y
1
to Y
4
, which are surface discharge electrodes, and these electrodes, except for the electrodes X
1
and X
5
at the two sides, i.e., the electrodes X
2
to X
4
and the electrodes Y
1
to Y
4
, are commonly used by display lines that are adjacent in the direction of the address electrodes. With this, the number of electrodes is almost halved and the pixel pitch can be reduced, achieving higher definition compared to the PDP shown in FIG.
30
. In addition, the scale of the drive circuit can also be halved.
However, in the publications cited above, since write is performed in linear sequence for the display lines L
1
to L
8
, the discharge would affect adjacent pixels in the direction of the address electrodes if the partitioning walls
191
to
199
are omitted, resulting in erroneous display. Thus, the partitioning walls
191
to
199
cannot be omitted and this presents an obstacle to achieving higher definition by reducing the pixel pitch. In addition, it is not easy to provide the partitioning walls
191
to
199
on the central lines of the electrodes and, as a result, the PDP
10
Q will be expensive to produce. Furthermore, in the publications mentioned above, a specific waveform of the voltage to be applied to the electrodes is not disclosed and, as a result, the invention has not been put into practical use. In order to make it possible to remove the partitioning walls running in the direction of the surface discharge electrodes, the distance between the electrodes at the two sides of each of the partitioning walls
191
to
196
must be increased in the structure shown in
FIG. 30
, so as to reduce the effect of their electric fields between that electrodes. Consequently, the pixel pitch increases, preventing achievement of higher definition. For instance, the distance between the electrodes Y
1
and X
2
(non display line) is 300 &mgr;m when the distance between the electrodes Y
1
and X
2
(display line) is 50 &mgr;m.
In addition, during the reset period, light is emitted because of the whole-screen (all pixel) discharge and brightness in the black display areas is increased, reducing the quality of the display.
Moreover, since the color of the phosphor is white or bright gray, incident light from the outside is reflected on the phosphor at non display lines when observing an image on the PDP in a bright place, lowering the contrast of the image.
In addition, since only one line can be addressed at a time, the address time cannot be reduced, and it is not possible to achieve a higher number of gradations by increasing the number of subfields or to achieve higher brightness by increasing the number of times the sustaining discharge is performed.
SUMMARY OF THE INVENTION
Accordingly, a comprehensive object of the present invention is to provide a plasma display panel, a method of driving same and a plasma display apparatus, all of which achieve a higher quality image.
To put it concretely, a first object of the present invention is to provide a method of driving a plasma display panel and a plasma display apparatus, which achieve higher definition by further reducing the pixel pitch.
A second object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase black display quality reduced by whole-screen (all pixel) discharge light emission during a reset period.
A third object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase image contrast by decreasing the reflected light from a non display line.
A fourth object of the present invention is to provide a plasma display panel, a method of driving the same and a plasma display apparatus that can increase the number of gradations and brightness by addressing plural display lines simultaneously to decrease the address period.
According to the first aspect of the present invention, there is provided a plasma display apparatus comprising: a plasma display panel having a substrate, electrodes X
1
to Xn+1 formed at the substrate, electrodes Y
1
to Yn formed at the substrate and address electrodes formed at the substrate or at another substrate facing the substrate at a distance, the electrodes X
1
to Xn+1 being arranged in that order and parallel to one another, an electrode Yi being arranged between an electrode Xi and an electrode X+1 for each i=1 to n, the address electrodes being arranged intersecting the electrodes X
1
to Xn+1 and Y
1
to Yn at a distance; and an electrode drive circuit; wherein the electrode drive circuit includes: first field addressing means, for i=1 to n, for causing a first address discharge to occur between the electrode Yi and the address electrodes selected in correspondence to display data in a first field of a frame and for causing a discharge to occur between the electrode Yi and the electrode Xi using the first address discharge as a trigger to generate a first wall charge required for a sustaining discharge in correspondence to the display data in the first field; first field sustaining means, after the first wall charge has been generated and for odd number o among 1
Asami Fumitaka
Hirose Tadatsugu
Ishii Tomoyuki
Kanazawa Yoshikazu
Kishi Tomokatsu
Awad Amr
Fujiitsu Limited
Greer Burns & Crain Ltd.
Jankus Almis R.
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