Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-11-12
2004-02-03
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000, C315S169100, C315S169200, C313S581000, C313S582000
Reexamination Certificate
active
06686897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a plasma display panel (hereinafter referred to as PDP) and a method of driving the PDP. More specifically, the method and apparatus of the present invention can reduce the back-glow phenomena caused by the discharge operation during the reset period for a PDP, therefore, enhancing the contrast of the plasma display panel
The present invention generally relates to a plasma display panel (hereinafter referred to as PDP). More specifically, it relates to a plasma panel can reduce the back-glow phenomena caused by the discharge operation during the reset period, therefore, enhancing the contrast of the plasma display panel.
2. Description of the Related Art
Plasma display is one of most promising flat panel display technologies because it can provide a large and flat display screen and can display full-color images. The basic theory and operation of a PDP is described below.
FIG. 1
is a cross-sectional view of a conventional PDP cell constructed by two glass substrates
1
and
7
and the components formed thereon. Inert gases, such as Ne and Xe, are filled in the cavity between the glass substrates
1
and
7
. The components formed on the glass substrate
1
include sustaining electrodes X, scanning electrodes Yi, a dielectric layer
3
and a protective film
5
. The components formed on the glass substrate
7
include address electrodes Aj and the fluorescent material
9
formed thereon. The rib
8
(generally which is parallel to the scanning electrodes Yi and the sustaining electrodes X) is formed on the peripheral of each PDP cell to isolate the PDP cell. Therefore, each PDP cell
10
includes three kinds of electrodes, i.e., the sustaining electrode X and the scanning electrode Yi, which is parallel to each other, and the address electrodes Aj crossing vertically the sustaining electrode X and the scanning electrode Yi.
FIG. 2
is a block diagram illustrating a plasma display formed by the PDP cells shown in FIG.
1
. As shown in the drawing, the PDP
100
is driven by the scanning electrodes Y
1
~Yn, the sustaining electrodes X and the address electrodes A
1
~Ap. The position of the cell
10
is as shown in the drawing. Each cell is isolated by the rib
8
as shown in FIG.
1
. Furthermore, the plasma display includes the control circuit
110
, the Y scanning driver
112
, the X sustaining driver
114
and the address driver
116
. The control circuit
110
generates timing signals for the drivers according to the external clock signal CLOCK, the data signal DATA, the vertical synchronous signal VSYNC and the horizontal synchronous signal HSYNC, wherein the clock signal CLOCK represents the data transmittal clock, the data signal DATA represents the display data, and the vertical synchronous signal VSYNC and the horizontal synchronous signal HSYNC are respectively used to define the timing sequences of a frame and a scanning line. The control circuit
110
sends the display data and the clock signal to the address driver
116
and sends the corresponding frame control clock to the Y scanning driver
112
and the sustaining driver
114
. The display data is sequentially transmitted to the address driver
116
by the control circuit
110
and wall charges are built to selected cell by the address discharges. Address discharges are caused by the data pulses of address electrodes A
1
~Ap and the scanning pulses of scanning electrodes Y
1
~Yn which are sequentially sent by the Y scanning driver
112
. The detailed operation and the control signals for the electrodes are described below.
FIG. 3
is a diagram illustrating the manner to drive a conventional PDP to display a frame. As shown in the drawing, each frame is divided into eight sub-fields SF
1
~SF
8
. Each sub-field includes three operating period, that is, the reset period R
1
~R
8
, the address period A
1
~A
8
and the sustain period S
1
~S
8
. In the reset period, the residual charges of the former sub-field are cleared to make the initial conditions of all cells before the address period almost the same. In the address period, the address discharges are initiated in the selected cells according to the display data and then wall charges are accumulated. In the sustain period, sustain discharges for displaying are repeatedly initiated and visible light can be produced in the cells which have accumulated charges through the address discharge in the address period. All of the PDP cells are processed at the same time during the reset period R
1
~R
8
and the sustain period S
1
~S
8
. The address operation is sequentially performed for each cell on the scanning electrodes Y
1
~Yn during the address period A
1
~A
8
. Moreover, the display brightness is proportional to the length of the sustain period S
1
~S
8
. In the example of
FIG. 3
, the length of the sustain periods S
1
~S
8
of the sub-fields SF
1
~SF
8
can be set in a ratio of 1:2:4:8:16:32:64:128 to display images in 256 gray scales.
FIG. 4
is a timing diagram of the voltage waveforms on the electrodes in a single sub-field of the prior art. The voltage waveforms on the address electrodes Aj are generated by the address driver
116
, the voltage waveforms on the sustaining electrodes X are generated by the X sustaining driver
114
, and the voltage waveforms on the scanning electrodes Y
1
~Yn are generated by the Y scanning driver
112
. As shown in the drawing, each sub-field includes the reset period, the address period and the sustain period. The voltage waveforms in each period and the resulted manners are described in detail below.
At the time point a (in
FIG. 4
) of the reset period, the voltage of the scanning electrodes Y
1
~n is set to 0 V, and a write pulse having a voltage of VS+VW is applied to the sustaining electrode X, in which the voltage VS+VW is larger than the firing voltage between the sustaining electrode X and the scanning electrode Yi. Therefore, the global writing discharge W occurs between the sustaining electrode X and the scanning electrodes Yi. This discharge process accumulates negative charges on the sustaining electrode X and positive charges on the scanning electrodes Yi. The electric field produced by the accumulated negative charges and the positive charges will cancel out the voltage difference between the sustaining electrodes, thus the time of global writing discharge W is very short.
At the time point b, the sustaining electrode X is set to 0 V, and a sustaining pulse
202
having a voltage of VS is applied to all of the scanning electrodes Y
1
~Yn, wherein the value of the voltage VS plus the voltage caused by the charges accumulated between the sustaining electrodes must be larger than the firing voltage between the scanning electrodes Yi and the sustaining electrode X. Thus, the global sustaining discharge S occurs between the sustaining electrode X and the scanning electrodes Yi. Different from the previous discharge process, this discharge process accumulates positive charges on the sustaining electrode X and negative charges on the scanning electrodes Yi.
At the time point c, the scanning electrode Yi is set to 0 V, an erase pulse
203
having a voltage lower than VS is applied to the sustaining electrode X, and an address pulse having a voltage of −VS can be applied to the address electrode Aj. The erase pulse is used to neutralize a part of the charges. On the scanning electrodes Y
1
~Yn, required wall charges are left so that the write operation can proceed with a lower voltage in the sequential address period.
In the address period, the voltage of the sustaining electrode X and the scanning electrodes Yi are pulled up to VS at the time point d. Then a scan pulse
204
is sequentially applied to the scanning electrodes Y
1
~Yn from the time point e, and an address pulse having a voltage of VA is applied to the address electrode Aj at the same time. When a cell of a scanning line turns ON, the write discharge occurs, that is, the corresponding display data is written into the cell.
After scanning all of
Huang Jih Fon
Lo Shin-Tai
AU Optronics Corp.
Ladas & Parry
Tran Henry N.
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