Plasma display panel

Electric lamp and discharge devices – With gas or vapor – Three or more electrode discharge device

Reexamination Certificate

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Reexamination Certificate

active

06639363

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a panel structure of a surface discharge scheme AC type plasma display panel.
The present application claims priority from Japanese Application No. 2000-363049, the disclosure of which is incorporated herein by reference for all purposes.
2. Description of the Related Art
In recent years, a surface discharge scheme AC type plasma display panel as an oversized and slim display for color screen has received attention, and is becoming widely available.
FIG. 7
is a front view schematically illustrating the cell structure of the surface discharge scheme AC type plasma display panel which has been previously proposed by the present applicant.
FIG. 8
is a sectional view taken along the V—V line of FIG.
7
.
The PDP illustrated in FIG.
7
and
FIG. 8
includes a front glass substrate
1
, serving as the display surface, having the back surface on which a plurality of row electrode pairs (X, Y) are arranged in parallel and extend in the row direction of the front glass substrate
1
(the lateral direction of FIG.
7
). Each of the pairs of row electrodes X and Y forms one display line (row) L of the matrix display.
The row electrode X is constructed of transparent electrodes Xa each of which is formed of a T-shaped transparent conductive film made of ITO (Indium Tin Oxide) or the like, and a bus electrode Xb formed of a metal film which extends in the row direction of the front glass substrate
1
and is connected to a narrow proximal end of each of the transparent electrodes Xa.
Likewise, the row electrode Y is constructed of transparent electrodes Ya each of which is formed of a T-shaped transparent conductive film made of ITO or the like, and a bus electrode Yb formed of a metal film which extends in the row direction of the front glass substrate
1
and is connected to a narrow proximal end of each of the transparent electrodes Ya.
The row electrodes X and Y are arranged in alternate positions in each display line L in the manner “X-Y” in one display line, “Y-X” in the next display line.
In each of the row electrode pairs (X, Y), each of the transparent electrodes Xa and Ya aligned along the corresponding bus electrodes Xb and Yb extends toward its counterpart in the paired row electrodes such that wide top ends of the paired transparent electrodes Xa, Ya face each other with a discharge gap g of a required width in between.
Each of the bus electrodes Xb and Yb has a double-layer structure with a black conductive layer on the display surface side.
On the back surface of the front glass substrate
1
, a black light absorption layer BS extends in the row direction between the back-to-back bus electrodes Xb of the respective row electrode pairs (X, Y) adjacent to each other and between the back-to-back bus electrodes Yb.
A dielectric layer
2
is also formed on the back surface of the front glass substrate
1
and covers the row electrode pairs (X, Y). Furthermore, an additional dielectric layer
2
A extends in the row direction and protrudes from the back face of the dielectric layer
2
at a position on the back face of the dielectric layer
2
opposite to the back-to-back bus electrodes Xb (back-to-back bus electrodes Yb) in adjoining pairs and opposite to a region between the back-to-back bus electrodes Xb (back-to-back bus electrodes Yb).
In turn, a protective layer
3
made of MgO is formed on the back faces of the dielectric layer
2
and additional dielectric layers
2
A.
The front glass substrate
1
is disposed in parallel to a back glass substrate
4
having a surface facing toward the display surface on which column electrodes D are arranged parallel to each other at predetermined intervals and each extend in a direction at right angles to the row electrode pair (X, Y) (the column direction) in a position opposite to the paired transparent electrodes Xa and Ya in each of the row electrode pairs (X, Y).
On the surface of the back glass substrate
4
on the display surface side, a white dielectric layer
5
covers the column electrodes D, and partition walls
6
are formed on the dielectric layer
5
.
The partition wall
6
is shaped in a ladder pattern with vertical walls
6
A each of which extends in the column direction in a position between the two parallel arranged column electrodes D, and transverse walls
6
B each of which extends in the row direction in a position opposite to the additional dielectric layer
2
A. The ladder-patterned partition wall
6
is provided for partitioning the discharge space S situated between the front glass substrate
1
and the back glass substrate
4
into areas, each facing the paired transparent electrodes Xa and Ya in each row electrode pair (X, Y), to form quadrangular discharge cells C.
The partition walls
6
partitioning the discharge space S are arranged in the column direction separated from each other by an interstice SL which extends in the row direction between the two partition walls
6
, that is, the interstice SL intervening between the mutually opposite transverse walls
6
B of the respective partition walls
6
adjacent to each other. The interstice SL is situated at a position opposing each region between the back-to-back bus electrodes Xb and between the back-to-back bus electrodes Yb.
A phosphor layer
7
is placed on all the five faces made up of the four side faces of the vertical walls
6
A and transverse walls
6
B of the partition wall
6
and one face of a dielectric layer
5
which face toward the discharge cell C. The phosphor layer
7
formed inside each discharge cell C has a red color (R), a green color (G) or a blue color (B) applied and the phosphor layers
7
are arranged in the order red (R), green (G) and blue (B) along the row direction.
The discharge cell C is filled with a discharge gas.
The protective layer
3
covering the additional dielectric layer
2
A is in contact with the face of the transverse walls
6
B of the partition walls
6
on the display surface side. Hence, as seen from
FIG. 8
, the additional dielectric layer
2
A provides a block between the adjacent discharge cells C in the column direction.
The PDP as described above displays images through the following procedure.
First, at the concurrent reset period, a reset pulse is applied to the row electrodes X or Y, to cause reset discharge between the column electrode D and the row electrode X or Y in each discharge cell C, which results in forming wall charge on the surface of the dielectric layer
2
in each discharge cell C.
Next, through the line sequential addressing operation in the addressing period, a scan pulse is applied to the row electrode Y to selectively cause opposite discharge (selective discharge) between the transparent electrode Ya and the column electrode D, which results in scattering lighted cells (the discharge cell in which the wall charge on the dielectric layer
2
is not erased) and nonlighted cells (the discharge cell in which the wall charge on the dielectric layer
2
is erased), in all the discharge lines L over the panel in accordance with the image to be displayed.
Then, at the sustain discharge period, a discharge sustain pulse is simultaneously applied alternately to the row electrodes X and Y in all the display lines, to cause surface discharge (sustain discharge) between the transparent electrodes Xa and Ya facing each other in each lighted cell.
The surface discharge in the lighted cell thus generates ultraviolet light. The generated ultraviolet light excites each of the phosphor layers
7
which have the three primary colors, red (R), green (G) and blue (B) applied in the respective discharge cells C, to allow them to emit light for forming a display image.
A feature of the above PDP is that interference may not occur between the discharges in the discharge cells C adjacent to each other in the row direction even when each discharge cell C is reduced in size in order for the screen to increase in definition, because the transparent electrode Xa, Ya of the row electrode X, Y extends from the bus electrode Xb, Yb t

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