Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-11-16
2004-12-28
Eisen, Alexander (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169400
Reexamination Certificate
active
06836261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an AC driving type plasma display driving method and apparatus.
2. Description of the Related Art
In recent years, plasma display panels (PDPs) have received a great deal of attention as a next-generation display device in place of CRTs because the PDPs are self-emission type display devices with good visibility, and can realize a low-profile large-screen display. In particular, an AC driving type PDP that can realize a large screen, is expected as a display device coping with high-quality digital broadcasting, and is demanded to attain higher image quality than the CRT.
FIG. 1
is a circuit diagram showing the whole arrangement of an AC driving type PDP apparatus. In
FIG. 1
, an AC driving type PDP
1
comprises scanning electrodes Y
1
to Yn and common electrodes X parallel to each other on one surface, and address electrodes A
1
to Am perpendicular to these electrodes Y
1
to Yn and X on the opposing surface. The common electrodes X are laid out close to the scanning electrodes Y
1
to Yn in correspondence with them, and have terminals commonly connected.
The common terminal of the common electrodes X is connected to the output terminal of an X driver
2
, the scanning electrodes Y
1
to Yn are connected to the output terminals of a Y driver
3
, and the address electrodes A
1
to Am are connected to the output terminals of an address driver
4
. The X driver
2
, Y driver
3
, and address driver
4
are controlled by control signals from a controller
5
.
The controller
5
generates the control signals on the basis of external display data D, clock CLK indicating the read timing of the display data D, horizontal sync signal HS, and vertical sync signal VS, and supplies the control signals to the X driver
2
, Y driver
3
, and address driver
4
.
FIG. 2
is a sectional view showing the structure of a cell Cij as one pixel on the i-th row and j-th column. In
FIG. 2
, a common electrode X and a scanning electrode Yi are formed on a front glass substrate
11
. The common electrode X and scanning electrode Yi are covered with a dielectric layer
12
for insulating them from a discharge space
17
, and the dielectric layer
12
is covered with a MgO (magnesium oxide) protective film
13
.
An address electrode Aj is formed on a rear glass substrate
14
facing the front glass substrate
11
, and covered with a phosphor
15
. Ribs
16
for preventing color mixing between cells and maintaining a discharge gap are formed at pixel boundaries on the rear glass substrate
14
and address electrode Aj. Ne+Xe Penning gas is sealed in the discharge space
17
between the MgO protective film
13
and phosphor
15
.
FIG. 3
is a voltage waveform chart showing an example of an AC driving type PDP driving method.
FIG. 3
shows one of the subfields constituting one frame. Each subfield is divided into a reset period comprising a full-surface write period and full-surface erase period, address period, and sustain discharge period.
In the reset period, all scanning electrodes Y
1
to Yn change to the ground level (0 V). At the same time, a full-surface write pulse of a voltage Vs+Vw (about 330 V) is applied to the common electrode X. At this time, all address electrodes A
1
to Am are at a potential Vaw (about 100 V). As a result, all cells on all display lines discharge to generate wall charges regardless of the preceding display state.
The potentials of the common electrode X and address electrodes A
1
to Am change to 0 V, and the voltages of wall charges themselves exceed the discharge start voltage in all cells to start discharging. During this discharge, since the electrodes do not have any potential difference, no wall charge is generated so that space charges self-neutralize to stop discharging. This is so-called self-erase discharge. This self-erase discharge makes all cells in the panel uniform freely from any wall charge. In this reset period, all cells can be made uniform regardless of the ON state of each cell in the preceding subfield. Thus, the next address (write) discharge can be stably performed.
In the address period, address discharges are done line-sequentially in order to turn each cell on/off in accordance with display data. More specifically, a scan pulse of −Vy level (about −150 V) is applied to the scanning electrode Y
1
corresponding to the first display line. At the same time, an address pulse of a voltage Va (about 50 V) is selectively applied to a cell that causes sustain discharge among the address electrodes A
1
to Am, i.e., the address electrode Aj corresponding to a cell to be turned on.
Consequently, a discharge occurs between the address electrode Aj and scanning electrode Y
1
of the cell to be turned on. Using this discharge as a priming effect (firing), the common electrode X of a voltage Vx (about 50 V) and scanning electrode Y
1
immediately discharge. Then, a sufficient amount of wall charges for the next sustain discharge are accumulated in the MgO protective film
13
on the common electrode X and scanning electrode Y
1
of the selected cell. The same processing is done for the scanning electrodes Y
2
to Yn corresponding to the other display lines, and new display data are written in all display lines.
In the sustain discharge period, a sustain pulse of a voltage Vs (about 180 V) is alternately applied to the scanning electrodes Y
1
to Yn and common electrode X to perform sustain discharges so as to achieve a video display of one subfield. Note that the length of the sustain discharge period, i.e., the number of sustain pulses determine the video luminance.
In the above driving method, each subfield in one frame has the reset period, and a full-surface write discharge by application of the full-surface write pulse is done in each subfield. For this reason, each subfield emits light in the reset period not originally contributing to the video display, which decreases the video display contrast.
To solve this problem, the present applicant has invented and filed a driving method that realizes high contrast by decreasing the number of full-surface write discharges per frame (Japanese Patent Application Laid-Open No. 313598/1993). According to this driving method, the full-surface write discharge in the reset period is executed in only part of subfields in one frame, and only erase discharges in the reset period are executed in the remaining subfields.
In this high-contrast driving method, an erase discharge is performed in the reset period of the next subfield SFn+1 immediately after the sustain discharge (sustain) period of the n-th subfield SFn, as shown in FIG.
4
. In this case, an erase pulse made of a small-width pulse (e.g., a pulse width of 2 &mgr;s or less) is applied to the common electrode X to erase wall charges of each electrode only from the cell which was turned on in the preceding subfield SFn.
An allowable range (voltage range from the minimum value to the maximum value will be called a driving voltage margin) is defined for the voltage values of various pulses for realizing driving of normally turning an ON cell on based on display data while keeping an OFF cell off. If the discharge starts unexpectedly early owing to nonuniform pixels and temperature condition changes in the small-width erase discharge during the reset period, a necessary wall charge erase fails. In addition, wall charges opposite in polarity to wall charges before an erase may be generated on the common electrode X and scanning electrode Y. This narrows the driving voltage margin.
To solve this problem, the present applicant has further invented and filed a new driving method (U.S. patent application Ser. No. 115911 filed on Jul. 15, 1998). According to this driving method, after a small-width pulse is applied during the reset period, another erase pulse (Slope Erase Pulse: SEP) which rises with a gradual slope is applied to make an erroneous erase state come close to a more complete erase state.
FIG. 5
shows an example of this driving method.
Kishi Tomokatsu
Nagaoka Keishin
Takamori Takahiro
Uchiyama Kouichirou
Eisen Alexander
Fujitsu Limited
Staas & Halsey , LLP
LandOfFree
Plasma display driving method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Plasma display driving method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plasma display driving method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3273667