Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-08-21
2004-08-31
Lao, Lun-Yi (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S062000, C345S067000, C345S068000, C345S210000, C315S169400
Reexamination Certificate
active
06784859
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display drive method. More particularly, the present invention relates to a technology to shorten the period of the address action.
The plasma display (PD) apparatus has good visibility because it generates its own light, is thin and can be made with a large-screen and high-speed display, therefore, it is attracting interest as a replacement for CRT displays.
FIG. 1
is a diagram that shows the basic structure of a PD apparatus.
As shown in
FIG. 1
, in a plasma display panel (PDP)
10
, X electrodes (the first electrode: sustain electrode) X1, X2, . . . , and Y electrodes (the second electrode: scan electrode) are arranged adjacently by turns and address electrodes (the third electrode) A1, A2, . . . are arranged in the direction perpendicular to that of the X and Y electrodes. A display line is formed between a pair of X electrode and Y electrodes, that is, between X1 and Y1, X2 and Y2, and so on, and a display cell (hereinafter simply referred to as cell) is formed at the point where a display line and an address electrode intersect.
The X electrodes are connected to an X sustain circuit
14
and the same drive signal is applied thereto. The Y electrodes are individually connected to a Y scan driver
12
and scan pulses are applied sequentially in the address action, which will be described later, otherwise the same address signal is applied thereto by a Y sustain circuit
13
. The address electrodes are connected to an address driver
11
, and an address signal to select ON cells and OFF cells is applied in synchronization with the scan-pulse in the address action, otherwise the same drive signal is applied. A control circuit
15
outputs a signal that controls each of the above-mentioned parts.
FIG. 2
is a diagram that shows the structure of a frame to describe the drive sequence in the PD apparatus. Since the discharge of the plasma display has only two states, that is, ON and OFF, the gradation of display is represented by the number of times of light emission. Therefore, a frame corresponding to a display is divided into plural subfields as shown in FIG.
2
. Each subfield comprises the reset period, the address period, and the sustain discharge period (sustain period). In the reset period, an action is carried out that brings all the cells, regardless whether the cell was ON or OFF in the previous field, into a homogeneous state, for example, a state in which wall charges are eliminated or wall charges are formed uniformly. In the address period, a selective discharge (address discharge) is carried out in order to determine the ON or OFF state of a cell according to the display data and wall charges needed to carry out a discharge for light emission in the next sustain period are formed in an ON state cell. In the sustain period, discharge is carried out repeatedly for light emission in the cell put into the ON state in the address period. The length of the sustain period, that is, the number of times of light emission differs from subfield to subfield, and the gradation of display can be represented by setting the number of times of light emission in a ratio, for example, 1:2:4:8 . . . , and combining subfields to emit light for each cell according to the gradation.
FIG. 3
is a waveform chart that shows an example of the conventional drive method of a plasma display panel. As shown schematically, in the reset period, a pulse of a voltage Vw larger than the discharge starting voltage, 300 V for example, is applied to the x electrode. The application of this pulse causes discharge in every cell regardless whether the cell was ON or OFF in the previous subfield and wall charges are formed. When this pulse is removed, discharge is caused again by the voltage of the wall charges themselves, but because there is no difference in potential between electrodes, the space charges generated by the discharge are neutralized and a homogeneous state without wall charges is realized. Although almost all charges are neutralized, a small amount of ions or metastable atoms remains in the discharge space. It may be a case that these remaining charges are used as pilot charges to cause the next address discharge, without fail. This is called, in general, the pilot effect or the priming effect. In the address period, a scan pulse is applied sequentially to the Y electrode and an address pulse (address signal) is applied to the address electrode of the cell to be turned ON in the display line to cause discharge. This discharge propagates to the X electrode side and wall charges are formed between the X electrode and the Y electrode. This scanning is performed over all the display lines. Next, sustain pulses of a voltage Vs (approx. 170 V) are applied repeatedly to the X electrode and the Y electrode in the sustain period. When the sustain pulses are applied, the cell in which wall charges are formed in the address period carries out discharge because the voltage of the wall charges is superposed on that of the sustain pulse and the total voltage exceeds the discharge starting voltage. The cell, in which no wall charge is formed in the address period, does not discharge.
The basic structure and action of the plasma display apparatus are described as above, and moreover various examples of modification have been proposed. In one of the modifications, for example, plural subfields with the same number of times of light emission are provided in the frame structure in
FIG. 2
to make an animation display smoothly. In another modification, a reset action is carried out only in the first subfield of a frame and not in the following subfields. In another modification, a reset is not carried out in all the cells but only in the cells that were ON in the previous subfield. In another modification, homogeneous wall charges are left in the reset action and the eliminative address method may be used to select cells that are OFF to eliminate wall charges in the address action. In another modification, a desired amount of charges is left, to use in the address action, by applying a voltage between the X electrode and the Y electrode from which the reset pulse is removed. Moreover, the present applicant has disclosed a structure in which homogeneous charges are left, on the entire surface, by designing the rise in voltage of reset pulse into an obtuse waveform so that the voltage changes gradually, in Japanese Unexamined Patent Publication (Kokai) No. 6-314078, and also in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835, the structure in which both the rise and fall of the reset pulse are designed as to be waveforms with a gradual slope. Furthermore, the applicant has disclosed the so-called ALIS method plasma display apparatus in which the number of display lines is doubled without changing the number of X electrodes and Y electrodes by forming display lines in every slit between the X electrodes and the Y electrodes, that is, between each Y electrode and both the X electrodes on both sides, in EP 0 762 373 A2.
As explained so far, there are various modifications of the plasma display apparatus, and the present invention can be applied to each one of them.
A high quality of display, which exceeds that of CRT, is required from the plasma display apparatus. The factors that will realize a high quality of display include the high definition, the high gradation, the high brightness, the high contrast, and so on. To achieve a high definition, it is necessary to increase the numbers of display lines and display cells by narrowing the pitch, and the above-mentioned ALIS method has a structure that enables the realization of a high definition at a low cost. To achieve a high contrast, it is necessary to decrease the intensity of discharge and the number of times of discharge, caused by the reset pulse, not relating to the display.
To achieve a high gradation, it is necessary to increase the number of subfields in the frame to increase the number of gradation levels that can be represented, but this also requires that the tim
Kishi Tomokatsu
Setoguchi Noriaki
Fujitsu Hitachi Plasma Display Limited
Lao Lun-Yi
Staas & Halsey , LLP
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