Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2003-02-25
2003-11-25
Philogene, Haissa (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169400, C345S066000, C345S063000, C345S067000, C313S585000, C313S584000
Reexamination Certificate
active
06653793
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a plasma display device utilizing a plasma display panel (PDP) for displaying an image and a method for setting operation of a driving circuit that drives the plasma display panel.
A plasma display device is becoming common place as a television set having a large screen. In order to promote making it more popular, it is necessary to improve performances of the plasma display device. Especially, it is an urgent necessity to improve a light emission efficiency that is defined by a ratio of luminance to power consumption, since it is lower than a liquid crystal display device at present.
2. Description of the Prior Art
As a color display device, a surface discharge AC type PDP is known well. The surface discharge type has a three-electrode structure in which first and second display electrodes that become anodes and cathodes in display discharge for determining light emission quantity of a cell are arranged in parallel on one of substrates, and address electrode are arranged on the other substrate so as to cross the display electrode pairs. The display electrode pairs are covered with a dielectric layer, and the address electrodes are opposed to the display electrodes via a discharge gas space. In the surface discharge type, fluorescent material layers for a color display are formed on the substrate on which the address electrodes are arranged so as to be apart from the display electrode pairs in the direction of the panel thickness. By making the fluorescent material layers apart from the display electrode pairs, deterioration of the fluorescent material layers due to the impact of discharge can be reduced.
As known well about a display by the AC type PDP, line sequential addressing is performed for controlling wall voltage of a cell in accordance with display data, and then a sustaining process is performed in which a sustaining voltage pulse train is applied to the cell. The addressing process determines which cells are lighted or unlighted, and the sustaining process determines light emission quantity of each cell. In the above-mentioned three-electrode structure, one of the display electrodes that make a pair and correspond to a row of a matrix display becomes a scan electrode for selecting a row in the addressing process. Address discharge between the scan electrode and the address electrode causes address discharge between the display electrodes, thereby wall charge are formed that is suitable for the sustaining process. In the sustaining process, a drive voltage having an alternating waveform is applied to the display electrode pair for all cells at one time, and display discharge of surface discharge form is generated along the surface of the substrate only in cells having a predetermined wall charge at that time (cells to be lighted).
Concerning a design of a drive voltage waveform for a PDP, Japanese unexamined patent publication No. 2001-242825 has proposed a method for determining a drive voltage for a reset process in which wall charge of a screen is equalized before the addressing process by utilizing a microdischarge start voltage closed curve (hereinafter referred to as a Vt closed curve). In this method, a potential state in a cell of a PDP having a plurality of electrodes is regarded as a point in a space with a coordinate system that is called a cell voltage plane. By measuring the microdischarge start voltage between electrodes of the PDP to be driven and by plotting the voltage in the cell voltage plane, the operating voltage characteristics are illustrated as a Vt closed curve. This illustration makes it easy to find out an optimal voltage condition in a real drive waveform. The cell voltage to be a coordinate axis of the cell voltage plane is defined by the sum of the voltage applied between electrodes by the driving circuit and a potential difference between electrodes (wall voltage) generated by the wall charge in a cell. In the case of the three-electrode structure, two of three interelectrodes are selected, and the cell voltage plane is defined by making each of cell voltage be a coordinate axis.
FIG. 14
shows a usual drive waveform in a conventional method for display discharge that is applied to a three-electrode structure. In the conventional driving method, a sustain pulse having a simple rectangular waveform of amplitude Vs is applied to the first display electrode and the second display electrode alternately during the display period. In other words, the first and the second display electrodes are biased to the potential −Vs temporarily and alternately. The address electrode is not biased. By this potential control, a drive voltage signal of a pulse train having alternating polarities is applied between the first display electrode and the second display electrode (i.e., to the XY-interelectrode). A voltage corresponding to a bias of the display electrode is applied between the first display electrode and the address electrode (i.e., to the XA-interelectrode) and between the address electrode and the second display electrode (i.e., to the AY-interelectrode). Responding to the application of the first sustain pulse to all cells, display discharge is generated in cells in which a predetermined wall charge has been formed in the previous addressing process. When the discharge is generated, the wall charge on the dielectric layer is erased, and soon reformation of wall charge starts. The polarity of the wall charge to be reformed is the opposite to the previous one. As the wall charge is reformed, the cell voltage at the XY-interelectrode drops so that the display discharge ends. The end of the discharge means that discharge current flowing through the display electrode becomes substantially zero. When the second sustain pulse is applied, display discharge is generated again since the polarity of the drive voltage is the same as the polarity of the wall voltage at that time point, and the cell voltage increases when the wall voltage is added to the drive voltage. After that, display discharge is generated similarly every application of the sustain pulse.
The pulse base potential is not necessarily the ground potential (GND). The polarity of the sustain pulse can be positive without being limited to the illustrated negative polarity. In addition, it is possible to apply a drive voltage signal similar to the illustrated one to the XY-interelectrode by applying a pulse having the amplitude Vs′ to one of the display electrodes and simultaneously applying a pulse having the amplitude —(Vs-Vs′) to the other display electrode.
FIG. 15
shows a cell voltage plane of a display process according to the conventional driving method. According to the cell voltage plane, a state transition of a cell can be understood. In
FIG. 15
, cell voltage Vc(XA) of the XA-interelectrode is assigned to the horizontal axis, and cell voltage Vc(AY) of the AY-interelectrode is assigned to the vertical axis. The states [
1
], [
1
′], [
2
], [
3
], [
3
′] and [
4
] shown with circles (∘) in
FIG. 15
correspond to time points t[
1
], t[
1
′], t[
2
], t[
3
], t[
3
′] and t[
4
] shown in
FIG. 14
, respectively.
When the second display electrode is biased to a negative potential, display discharge is generated with the first display electrode being an anode. After this display discharge finished, the application of the drive voltage (Vs) to the XY-interelectrode still continues during the period till the trailing edge of the pulse. Therefore, the space charge is attracted in electrostatic manner by the dielectric layer to be wall charge. This electrification phenomenon continues until the cell voltage Vc(XY) at the XY-interelectrode becomes zero. The wall voltage Vw(XY) at the XY-interelectrode at the end of the electrification phenomenon is −Vs. The state transition is performed from this state as following (1)-(4).
(1) In
Hashimoto Yasunobu
Itokawa Naoki
Seo Yoshiho
Fujitsu Limited
Philogene Haissa
Staas & Halsey , LLP
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