Planarizing glass layer spaced from via holes

Details Planarizing glass layer spaced from via holes Planarizing glass layer spaced from via holes

1992-02-28

1995-01-24

Larkins, William D.

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

257510, 257635, 257637, 257638, 257641, H01L 2946, H01L 2954, H01L 2962

Patent

active

053844831

ABSTRACT:
A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit. A second masking layer having openings which define the locations of the contact vias to be created is then formed over the second insulating layer. The size of the openings in the second masking layer are smaller than the size of the openings in the first masking layer. The contact vias are then formed through the first and second insulating layers.

REFERENCES:
patent: 3383568 (1968-05-01), Cunningham
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4489481 (1984-12-01), Jones
patent: 4675984 (1987-06-01), Hsu

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