Abrading – Machine – Rotary tool
Reexamination Certificate
1998-03-31
2001-01-09
Hail, III, Joseph J. (Department: 3723)
Abrading
Machine
Rotary tool
C451S041000, C451S288000
Reexamination Certificate
active
06171180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to using an abrasive surface and a particle-free liquid to polish a dielectric, wherein the dielectric is deposited within an isolation trench and across a polish stop surface such that a recess region of the dielectric is spaced below the polish stop surface.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. Numerous active devices are first placed within and upon a single semiconductor substrate. Those devices built into the substrate are separated or “isolated” from each other by dielectric structures. Select devices are interconnected by conductors which extend over an interlevel dielectric that isolates those devices. Contact areas are placed through the interlevel dielectric to electrically link the interconnect routing to select devices. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography. Isolation of the multiple interconnect levels and of the active devices from each other is necessary to provide for the fabrication of a reliable integrated circuit.
Unfortunately, unwanted surface irregularities (i.e., elevational disparities) occur across the topological surface of an integrated circuit during the formation of each level of the circuit. For example, an isolation dielectric formed on a topography of an integrated circuit may contain elevationally raised and recess regions. In particular, the upper surface of a trench isolation structure formed within, e.g., a silicon-based substrate, may contain elevational disparities which contribute to the non-uniformity of the isolation structure depth and/or thickness. Relatively shallow trench isolation structures are typically formed within the semiconductor substrate to isolate impurity regions of active devices placed in the substrate. If left unattended, elevational disparities in each level of an integrated circuit can lead to various problems. For example, when an interconnect is placed across a dielectric having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation using optical lithography may be difficult. Lithography involves using an optical system to expose certain areas of a photosensitive material (i.e., photoresist) to radiation. The depth-of-focus of the optical system may vary depending on whether the photoresist resides in an elevational “hill” or “valley” area, causing images projected onto the photoresist to be skewed in lateral dimension.
The concept of utilizing chemical and mechanical abrasion to planarize or remove the surface irregularities of a topological surface is well known in industry as chemical-mechanical polishing (“CMP”). As shown in
FIG. 1
, a typical CMP process involves placing a semiconductor wafer
12
face-down on a polishing pad
14
which is fixedly attached to a rotatable table or platen
16
. Elevationally extending features of semiconductor wafer
12
are positioned such that they contact the slurry attributed to the CMP process. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad
14
and semiconductor wafer
12
may be rotated while a carrier
10
holding wafer
12
applies a downward force F upon polishing pad
14
. An abrasive, fluid-based chemical, often referred to as a “slurry”, is deposited from a conduit
18
positioned above pad
14
upon the surface of polishing pad
14
. The slurry becomes positioned in the space between pad
14
and the surface of wafer
12
. The slurry initiates the polishing process by chemically reacting with the surface material being polished. The rotational movement of polishing pad
14
relative to wafer
12
causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer
12
. The abrasive slurry particles are typically composed of silica, alumina, or ceria.
Delivery of the slurry must be carefully monitored to ensure that the slurry does not unduly accumulate in select regions of the topography. If too much slurry accumulates in a relatively small area, that area may scratch the underlying surface or, in the extreme, polish at an unacceptably high polish rate. A post-CMP cleaning step is required to remove residual slurry particles from the surface of the polished topography. Without adequately removing the slurry, abrasive slurry particles will remain on the semiconductor topography and contaminate that surface. Considering the minute dimensions of integrated circuit topological features, even the tiniest of defect in the semiconductor topography can render the ensuing integrated circuit inoperable. Unfortunately, the removal of such slurry particles may be time consuming and costly. Further, some types of cleaning procedures can be detrimental to the semiconductor topography. The slurry waste must also be disposed of and subjected to waste treatment after planarization is complete because of the toxic nature of some of the effluent components. The disposal and waste treatment of the slurry effluent significantly increases the cost of manufacturing the integrated circuit.
FIGS.
2
-
5
illustrate the formation of a trench isolation structure within a semiconductor substrate, according to a conventional technique. As shown in
FIG. 2
, a semiconductor substrate
20
comprising, e.g., lightly doped single crystalline silicon is provided. A silicon nitride (“nitride”) layer
24
is arranged across the upper surface of substrate
20
. A “pad” oxide layer
22
may be interposed between substrate
20
and nitride layer
24
to reduce inherent stresses between nitride and silicon. As shown, portions of nitride layer
24
and substrate
20
are etched away to define a trench
26
within substrate
20
. Turning to
FIG. 3
, fill oxide
28
(i.e., silicon dioxide) is then deposited into trench
26
to a level spaced above the upper surface of nitride layer
24
using chemical-vapor deposition (“CVD”). Prior to depositing fill oxide
28
, a thermally grown oxide liner may be formed at the periphery of trench
26
while nitride layer
24
protects the upper surface of silicon-based substrate
20
from being oxidized. The resulting upper surface of fill oxide
28
includes a recess region
30
elevationally raised above the trench area. A CMP step is then performed to planarize the surface of the semiconductor topography. The thickness, t
1
, of the fill oxide
28
above nitride layer
24
must be sufficiently large e.g., 6,000 Å, to ensure that recess region
30
does not extend below the uppermost surface of substrate
20
. Otherwise, portions of substrate
20
would have to be removed to achieve complete planarization of fill oxide
28
, causing contamination of the substrate “active areas” beneath nitride layer
24
. Moreover, ensuing impurity regions implanted into the active areas would not receive an optimal dosage and/or implant profile. In the extreme, implant regions might extend below the base of fill oxide
28
, undesirably permitting current leakage between isolated active areas. Unfortunately, forming a relatively thick fill oxide
28
above nitride layer
24
means that the time period required for the deposition of fill oxide
28
can be rather lengthy. As such, preventing recess region
30
from extending below the uppermost surface of substrate
20
may be achieved at the expense of a loss in the throughput and an increase in the costs of an integrated circuit manufacturer.
FIG. 4
illustrates the formation of a trench isolation structure
32
comprising fill oxide
28
formed exclu
Kallingal Chidambaram G.
Koutny, Jr. William W. C.
Ramkumar Krishnaswamy
Conley Rose & Tayon
Cypress Semiconductor Corporation
Daffer Kevin L.
Hail III Joseph J.
Hong William
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